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Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik

punechips — Thu, 21 Jul 2011 10:48:56 +0000

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik
When: July 30, 2011 from 10:30 am to 12:00 noon
Where: Venture Center, NCL Innovation Park, Pashan Road

PCI Express Architecture and Applications for FPGAs

Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI Express^TM. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running Windows^TM, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.

About the speaker: Kiran Puranik

Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.

Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business

punechips — Mon, 11 Jul 2011 06:07:14 +0000

photo credit: Patrick Hoesly

Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.

Click here to download the PDF.

This event is jointly brought to you by PuneChips and LSI Corporation.

What: Technical Talk by Dr. T.R. Ramachandran on Building and Autonomoous and Scalable Semiconductor VLSI Business
Where: Sargam Auditorium, 4th floor, LSI India Research & Development Private Limited, T +91 20 4010 4700
When: Wednesday, July 13th 2011, 9:30am-11am. Please arrive by 9:00am for security registration and snack

RSVP: Reshma Arthani: Reshma.Artani@lsi.com, Mobile: +91.992.320.3557

Abstract:

The presentation focuses on effective ways to build autonomous and scalable semiconductor VLSI businesses. The trends in the VLSI industry and inherent challenges of growth make autonomy & scale-building essential elements of long-term success. This is particularly relevant to emerging geographies like India where there is increased focus on enhancing end-to-end capabilities and overall management.

About the speaker:

T. R. Ramachandran is Senior Director for Product Operations in the Storage Peripherals Division at LSI. In this role, he reports to the Senior Vice President and General Manager of the division and is responsible for the operations infrastructure, business processes, IP and customer program management across the entire product lifecycle from planning through manufacturing ramp for LSI’s highest volume semiconductor business. Before assuming this role, TR held a number of positions in LSI where he brought to bear a unique blend of expertise in a range of areas from business, operations & program management, strategic/competitive analysis, large-scale M&A and business transformations, global product development and deployment, and supplier & manufacturing management. He lives in the United States in Northern California, and is keenly interested in various aspects of technology & broader public policy as well as problems of scale tied to private, public and/or non-governmental sectors.

TR received a Bachelor’s degree in Metallurgical Engineering from IIT-M (Indian Institute of Technology in Madras/Chennai) and is a recipient of the Dr. Dhandapani Prize from IIT-M and the Vidya Bharati Prize conferred by the Indian Institute of Metals. He received his Masters and Ph.D. degrees in Materials Science from the University of Southern California, Los Angeles. His Ph.D. was focused on structural and optical studies of semiconductor thin films & quantum dot nanostructures and innovative forays into nanotechnology using scanning probe microscopes.

FPGA Virtual Summit is here again

punechips — Wed, 01 Jun 2011 05:52:47 +0000

This year’s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please visit for information. Click here for registration.

Continue reading FPGA Virtual Summit is here again

Event: Digital Design and Prototyping with Verilog by Mr. Basu on April 28, 2011

punechips — Tue, 19 Apr 2011 06:25:46 +0000

photo credit: oskay

What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu
When: April 28, 2011 from 9:00 am to 6:00 pm
Where: Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008

This event is not free. The fee is Rs. 1000 per person, which is hardly anything in our opinion. You can get a 25% discount if you bring your own laptop and a further 25% discount with a valid student ID. I want to encourage everyone interested to attend this seminar even though it is not free. Please call +91 20 2590 2984 to register. You can view the workshop details here.

About the Speaker
Mr Basu is a Design Engineer with experience in both Digital and Analog Design using a multitude of EDA and simulation tools. He has strong interests in Embedded systems design and multicore code design. He is a Hobby Robotics fan and entrepreneur in a related field. He has a B.Tech (H) ’03 and M.Tech ’04 from Indian Institute Of Technology , Kharagpur.

He was the Component Design Engineer for Intel India’s first Multicore project where he also co-authored the Enhanced
Structural Tester Based Functional Test methodology for Intel Multicore processors. He was also the Mixed-Signal Design
Consultant for National Semiconductor’s Sponsored Project at IIT Kharagpur.

He is an accomplished researcher and speaker. A few of his research projects include:

Behavioral Modelling for Mixed Signal Sytems using Verilog-AMS speeding up simulation times by 1000x
Analysis of spice simualtion engine for simulation speedup
Multi-core programming using Message Passing Interface and CUDA

Previously, he has done similar seminars on Behavioral Modelling at IIT Kharagpur

Free Event: Advanced System Verilog Tips Including OVM & UVM Tips by Cliff Cummings

punechips — Sun, 10 Apr 2011 14:35:06 +0000

SystemVerilog Guru Cliff Cummings is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to re-engage with him. This event is completely free, but registration is required. Please visit this link to register and view the agenda.

This event is co-sponsored by Qlogic and Cadence who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.

Mobile Networks – Moving from 3G to 4G

punechips — Thu, 24 Feb 2011 07:22:42 +0000

photo credit: kalleboo

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Gandhar Gokhale on Moving from 3G to 4G
When: Saturday, 26th March 2011, 10:30 am to 12:00 noon.
Where: Venture Center, Classroom E, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Mobile Networks - Moving from 3G to 4G
This presentation will be an introduction to the mobile network evolution. It’ll run through the evolution of generations of mobile networks to the upcoming 4G. The radio interface and terrestrial network evolution in each generation will be briefly touched upon. The LTE (Long Term Evolution) as the candidate technology for 4G shall be explored. We’ll conclude by discussing how these generations have impacted or shall impact our lives.

About the Speaker – Gandhar Gokhale
Gandhar Gokhale is a software architech with LSI Corporation. He has more than 12 years of Network Software development and Network Security experience. He completed his M.E. (Telecom) from IISc Bangalore and B.E. (Electronics) from WCE Sangli.

Event: Storage and Networking Protocols for the Next Generation

punechips — Tue, 05 Oct 2010 17:06:35 +0000

PuneChips Event: Storage and Networking Protocols for the next generation

This is a PuneChips event

What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)

Registration and Fees: This is a FREE event. Seating is limited. To attend, please RSVP: sulekha.thakkar@qlogic.com.

For more details on Howard’s talk, please see the attached flier.

This event is sponsored by QLogic, a global leader and technology innovator in high performance networking, and supported by ISA (Indian Semiconductor Association), the premier trade body Indian Electronic System Design and Manufacturing Industry.

PuneChips is the forum for semiconductor, EDA and applications designers in and around Pune. It was formed to foster an environment for the growth of semiconductor, EDA and applications companies in and around Pune. For more details, visit our website at www.punechips.com. If you wish to contribute to the community, please join the PuneChips group on groups.google.com. You can also join the PuneChips group on LinkedIn.

Please forward this e-mail to anyone in Pune interested in semiconductors, chip design and verification, VLSI design, and embedded design.

Event: Electronic Packaging – Materials and Mechanics Challenges

punechips — Fri, 02 Jul 2010 12:54:47 +0000

Photo courtesy of Exponent, Inc.

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Dr. Sandeep Sane on Electronic Packaging – Materials and Mechanics Challenges
When: Saturday, 10th July 2010, 10:30 am to 12:30 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Electronic Packaging – Materials and Mechanics Challenges
Electronic packaging has typically been defined as providing an enabling function and a space transformer between the IC feature sizes and the board & system level interconnects and over years it has grown to become a ubiquitous part of the overall electronic assembly. In certain market segments, such as flash memories, the package has evolved to become a key product differentiator and performance enabler. The scope of electronic packaging is very broad across multiple application areas such as CPU’s and Chipsets for the desktop, mobile and server segments, hand-held and wireless devices, telecom components & network processors, and memory devices; with each segment potentially having its unique set of demands and constraints such as the form factor, function, cost, reliability requirements, thermal and electrical performance.

To ensure that right technical and cost-effective solutions are defined, developed and deployed across the different market segments, electronic packaging provides significant research and development challenges and opportunities across multiple disciplines including materials, mechanics, reliability, thermals, high speed interconnects, power delivery and manufacturing.

This presentation will first provide an overview of current and future package technologies and associated demands in the different market segments, followed by focusing on some of the recent progress made in addressing some of the mechanics and materials challenges and highlight opportunities in future packaging technology development.

About the speaker – Dr. Sandeep
Sandeep Sane received his Ph.D. from California Institute of Technology, Pasadena in Aerospace Engineering with major in Solid Mechanics. He holds M.S. in Aeronautics, California Institute of Technology and B.Tech in Mechanical Engineering from Indian Institute of Technology, Bombay (Mumbai).

Sandeep is currently a Technology Development manager in the Assembly and Test Technology Development (ATTD) organization, Intel Corp., Chandler. He manages a technical team of 30 engineers including an experimental mechanics laboratory; equipped with start of art analysis and validation metrologies. His team is chartered to deliver fundamental understanding of various mechanical issues in electronic packaging, establish roadmaps for ATTD and work directly with Intel’s customers (OEM/ODMs) and suppliers to resolve mechanical issues. He is also responsible for delivering novel mechanical analysis, material characterization and validation techniques to help optimize design, material and process changes to deliver reliable and cost effective solutions for Intel’s packaging technologies. Sandeep has led and participated in numerous taskforces and management review boards to resolve critical issues in a timely manner impacting Intel’s bottom-line. Prior to joining Intel, he was a Development Staff Engineer with IBM, Endicott, NY, working in Mechanical & Thermal Analysis group.

Sandeep has filed for more than 15 patents and have published several technical articles in various conferences and journal proceedings. He is also a recipient of numerous awards across Intel for his technical contributions. He is a member of ASME, IEEE and an active member of organizing committees for ASME and IEEE conferences. He also serves on Industrial Advisory Board for Mechanical Engineering at University of Colorado, Boulder and NSF review committee.

About Venture Center
Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips
PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips. Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

Event: InCSIghts 2010 Panel on Future Devices and Convergence

punechips — Fri, 26 Mar 2010 09:53:21 +0000

What: Panel discussion on Future Devices and Convergence as a part of InCSIghts 2010 organized by Computer Society of India, Pune Chapter
When: Saturday, 27th March 2010, 2:00 pm to 3:30 pm.
Where: Suman Mulgaonkar Auditorium, ICC Towers, Senapati Bapat Road, Pune 411016
Registration and fees: This is a paid event. Registration is required.

About InCSIghts:

InCSIghts is the annual CSI IT roundup and will be held this year on March 27, 2010. The event will showcase a broad range of topics that IT professionals and academicians shouldn’t miss.

This event will try to give audiences a sneak peek into technologies that will dominate the future and analyze their impact on IT professionals. It will also focus on issues relevant to industry needs today, both business and technical. InCSIghts is Pune’s premier annual event that delivers an informative and actionable perspective of the issues shaping our industry with a peek at the future of technology. This year, InCSIghts brings you some of the most respected names on Pune’s IT scene with a cuisine of thought-provoking items on the agenda.

We have planned four sessions this year – Technology, e-Governance, Computer Science Research and Future of Mobile Devices and Convergence. Here are details:

Future of Devices and Convergence:

A new breed of mobile devices that offer tremendous productivity boost to the average user is just around the corner. As we are just starting to get used to the ubiquity of constantly connected mobile smart phones, future mobile devices promise a significantly enhanced feature set over the existing ones. Devices such as the iPad from Apple, Kindle from Amazon or the Adam from Notion Ink are some examples that highlight this new trend.

These advances bring new challenges to the software development community which has hitherto been focused on programming for personal computers. It is quite obvious that the software developers must embrace new trends in order to survive and prosper. This panel discussion is the ideal setting to start the conversation between the hardware makers and the software developers, as the focus of the discussion will be on various technologies/platforms/form-factors that will be prevalent in newer devices. The attendees can expect a spirited discussion on the following topics:

1) Awareness of current and future technologies/platforms/form-factors

2) Consideration on power, usability, ubiquity which are not that important in PC programming

3) Programming platforms and programming tools

4) Marketing your software product

5) Considerations for building the hardware

Contact:

Please write to:

Continue reading Event: InCSIghts 2010 Panel on Future Devices and Convergence

Event: Wavelet Transform & its Applications in Image Processing

punechips — Mon, 01 Mar 2010 12:02:24 +0000

image credit: Alessio Damato

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA.

What: Talk by Ganesh Bhokare on Wavelet Transform & its Applications in Image Processing
When: Saturday, 6th March 2010, 10:00 am to 12:00 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road
Registration and fees: This event is *FREE* for all to attend. No registration required.

Wavelet Transform & its Applications in Image Processing
In today’s multimedia wireless communication , major issue is bandwidth needed to satisfy real time transmission of audio and video data. The solution to this problem is to efficiently compress audio and video data for a given SNR. Wavelet transform is an evolving technology which offers far higher degrees of data compression compared to standard transforms such as DCT etc. In this talk we will be discussing concepts of wavelet transform and its applications to image compression and processing. The same can be extended to video processing.

About the speaker – Ganesh Bhokare
Ganesh Bhokare has over 15 years experience in using DSP audio, video and Embedded systems for Digital Media Processing. He is a PhD candidate at IIT Mumbai and currently in the process of defending his thesis. He has professional experience with NXP, Conexant, TI and Cirrus Logic.