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	<title>Pune&#039;s Semi/EDA &#38; Embedded Forum &#187; event</title>
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		<title>Free Event: Unified Data Center Network by Robert W. Kembel</title>
		<link>http://punechips.com/free-event-unified-data-center-network-by-robert-w-kembel/</link>
		<comments>http://punechips.com/free-event-unified-data-center-network-by-robert-w-kembel/#comments</comments>
		<pubDate>Mon, 19 Mar 2012 06:40:17 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
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		<description><![CDATA[<p>This <a href="../">PuneChips </a>event is brought to you by Qlogic and Solutions Technologies. PuneChips is a forum for Pune people interested in semiconductors design/apps/EDA in and around Pune.</p>
<p>What: Talk by Robert W. JKembel on Unified Data Center Network<br />
When: Wednesday, 21st March, 2012, 5 pm to 8 pm.<br />
Where: Yashada, Rajbhavan Complex, Baner Road, Pune</p>
<p><a href="http://punechips.com/free-event-unified-data-center-network-by-robert-w-kembel/" [...]<br />
<p>Continue reading <a href="http://punechips.com/free-event-unified-data-center-network-by-robert-w-kembel/">Free Event: Unified Data Center Network by Robert W. Kembel</a></p>]]></description>
			<content:encoded><![CDATA[<p>This <a href="../">PuneChips </a>event is brought to you by Qlogic and Solutions Technologies. PuneChips is a forum for Pune people interested in semiconductors design/apps/EDA in and around Pune.</p>
<p>What: Talk by Robert W. JKembel on Unified Data Center Network<br />
When: Wednesday, 21st March, 2012, 5 pm to 8 pm.<br />
Where: Yashada, Rajbhavan Complex, Baner Road, Pune</p>
<p>Registration and fees: This event is *FREE* for all to attend. Please RSVP to amarjeet.sharma@qlogic.com.</p>
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		<title>Nvidia Tech Week Open House &#8211; February 25/26, 2012</title>
		<link>http://punechips.com/nvidia-tech-week-open-house-february-2526-2012/</link>
		<comments>http://punechips.com/nvidia-tech-week-open-house-february-2526-2012/#comments</comments>
		<pubDate>Tue, 28 Feb 2012 15:53:27 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
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		<guid isPermaLink="false">http://punechips.com/?p=305</guid>
		<description><![CDATA[<p><a href="http://punechips.com/wp-content/uploads/2012/02/ws_NVidia-Graphics_3D_1152x864.jpg"><img class="alignnone size-medium wp-image-306" title="" src="http://punechips.com/wp-content/uploads/2012/02/ws_NVidia-Graphics_3D_1152x864-300x225.jpg" alt="Nvidia Graphics" width="300" height="225" /></a></p>
<p>I was invited to visit the Nvidia Tech Week this past weekend (February 25-26, 2012) at their facilities in Pune. This is a great concept &#8211; getting employees to invite friends and relatives to actually see what their company is all about is very good social outreach and a fantastic marketing initiative. If more tech companies in the area do similar events once or twice a year, it will help lift the shroud of technical opaqueness around them. I think hosting similar events in area colleges will also help students realize that even VLSI/Embedded Systems Design is cool.</p>
<p><a href="http://punechips.com/nvidia-tech-week-open-house-february-2526-2012/" [...]<br />
<p>Continue reading <a href="http://punechips.com/nvidia-tech-week-open-house-february-2526-2012/">Nvidia Tech Week Open House &#8211; February 25/26, 2012</a></p>]]></description>
			<content:encoded><![CDATA[<p><a href="http://punechips.com/wp-content/uploads/2012/02/ws_NVidia-Graphics_3D_1152x864.jpg"><img class="alignnone size-medium wp-image-306" title="" src="http://punechips.com/wp-content/uploads/2012/02/ws_NVidia-Graphics_3D_1152x864-300x225.jpg" alt="Nvidia Graphics" width="300" height="225" /></a></p>
<p>I was invited to visit the Nvidia Tech Week this past weekend (February 25-26, 2012) at their facilities in Pune. This is a great concept &#8211; getting employees to invite friends and relatives to actually see what their company is all about is very good social outreach and a fantastic marketing initiative. If more tech companies in the area do similar events once or twice a year, it will help lift the shroud of technical opaqueness around them. I think hosting similar events in area colleges will also help students realize that even VLSI/Embedded Systems Design is cool.</p>
<p>I was given a personal tour by Sandeep Sathe, a Sr. Development manager at Nvidia and also met with Jaya Panvalkar, Sr. Director and head of Pune facilities. There was enough to see and do at this event and unfortunately I was a bit short on time. It would have taken a good two hours for a complete walk-through, so I decided to spend more time on the GPU/HPC section though the Tegra based mobile device section was also quite impressive. It&#8217;s been a while since I actually installed a new graphics card in a desktop (actually, it&#8217;s been a while since I used a desktop), but graphics cards have come a long way! Nvidia is using standard PCI Express form factor cards for the GPU modules with on-board fans and DVI connectors.</p>
<p>The following are key takeaways from the demo stations I visited</p>
<p><strong>GeForce Surround 2-D</strong><br />
Here, Nvidia basically stretches the game graphics from a single monitor to three monitors. Great for gamers as it gives a fantastic feel for peripheral vision. The game actually doesn&#8217;t have to support this. The graphics card takes care of it. The setup here is that while the gamer sits in front of the main monitor, he also sees parts of the game in his peripheral vision in two other monitors that are placed at an angle to the main monitor. I played a car rally game and the way roadside trees, objects moved from the main monitor to the peripheral vision monitors was quite fascinating.</p>
<p><strong>GeForce 3-D Vision Surround</strong><br />
This is similar to the above, but with 3D. You can completely immerse yourself in the game. This sort of gaming setup is now forcing monitor manufacturers to develop monitors with ultra small bezel widths. I suppose at some point in the next few years, we will be able to seamlessly merge graphics from different monitors into one continuous collage without gaps.</p>
<p><strong>Powerwall Premium Mosaic</strong><br />
Powerwall is a eight monitor setup driven by the Quadro professional graphics engine. Two Quadro modules fit into one Quadroplex industrial PC to drive four monitors. Projectors can also be used in place of monitors to create a seamless view. The display was absolutely clear and highly detailed. The Powerwall is application transparent. Additional coolness factor &#8211; persistence data is saved so you don&#8217;t lose the image during video refresh and buffer swaps. This is most certainly a tool intended for professionals who need high quality visuals and computing in their regular work. Examples are automotive, oil and gas, stock trading.</p>
<p><strong>PhysX Engine</strong><br />
PhysX is a graphics engine that infuses real time physics into games or applications. It is intended to make objects in games or simulations move as they would in real life. To me this was very disruptive, and highlight of the show. You can read more about PhysX <a title="Nvdia PhysX Engine" href="http://www.nvidia.com/object/physx_faq.html" target="_blank">here</a>. It is very clear how PhysX would change gaming. The game demo I watched had several outstanding effects: dried leaves moving away from the character as he walks through a corridor, glass breaking into millions of shards as it would in real life. Also running was a PhysX simulation demo that would allow researchers to actually calculate how objects would move in case of a flood. What was stunning was that the objects moved differently every time as they would in real life. PhysX runs on Quadro and Tesla GPUs. It is interesting to note that Ra.One special effects were done using PhysX.</p>
<p><strong>3D photos and movies</strong><br />
Next couple of demos demonstrated 3D TV and photo technology using Sony TVs and a set of desktops/laptops. Notably, the Sony 3D glasses were much more comfortable compared to others. Nvidia is working with manufacturers to create more comfortable glasses. There was also a Toshiba laptop that uses a tracking eye camera to display a 3D image to the viewer regardless of seating position without glasses. It was interesting. However, the whole 3D landscape need a lot of work from the industry before it can become mainstream.</p>
<p><strong>Optimus</strong><br />
What was explained to me was that Optimus allows laptops to shut off GPUs when they are not needed. They can be woken up when high performance work is required. This would be automatic and seamless, similar to how power delivery is in on a Toyota Prius. This sort of a technology is not new to computing &#8211; a laptop typically puts a lot of components to sleep/hibernate when not being used, but the GPU is not included.</p>
<p><strong>Quadro Visualizations</strong><br />
This allows 2D/3D visualizations for automotive, architectural and similarly complex systems for up to one thousand users at a time. You can easily change colors, textures, views so everyone can comment and give constructive feedback. I was not sure if the design can be changed on the fly as well. Nvidia is working with ISVs like Maya and Autodesk on this.</p>
<p><strong>Tesla</strong><br />
Tesla GPUs use chips that are used for high performance computing and not rendering, which is different from what Nvidia typically does. The Tesla modules do not have any video ports! It has a <a title="Nvidia Tesla" href="http://www.nvidia.in/page/gpu_computing.html" target="_blank">heterogeneous GPU/CPU architecture</a> that saves power. In fact, the SAGA-220 supercomputer, dubbed India&#8217;s fastest, at ISRO&#8217;s Vikram Sarabhai Space Center facility uses 2070 Tesla GPUs along with 400 Intel Xeon processors. In addition to supercomputing, Tesla is very useful in 3D robotic surgery, 3D ultrasound, molecular dynamics, oil and gas, weather forecasting and many more applications.</p>
<p><strong>Tegra Mobile Processor</strong><br />
Next few demos showcased the Tegra mobile applications processor based on ARM Cortex A9 cores. The HD quality graphics and imaging were impressive. It is clear that smartphones and tablets of the day are clearly far more powerful compared to desktops of yesteryear and can support highly impressive video and audio in a very handy form factor.</p>
<p>In all, I had a great time. As I mentioned earlier, Nvidia along with other tech companies in Pune should hold more of these kinds of events to give technology exposure to the larger population in general. I think it is important for people to know that the stuff that makes Facebook run is the real key and that is where the coolness is.</p>
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		<title>Saankhya Labs nominated for EETimes ACE Awards</title>
		<link>http://punechips.com/saankhya-labs-nominated-for-eetimes-ace-awards/</link>
		<comments>http://punechips.com/saankhya-labs-nominated-for-eetimes-ace-awards/#comments</comments>
		<pubDate>Thu, 23 Feb 2012 09:54:53 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[ASIC]]></category>
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		<guid isPermaLink="false">http://punechips.com/?p=298</guid>
		<description><![CDATA[<p><a href="http://punechips.com/wp-content/uploads/2012/02/295620-2012_ACE_Awards.png"><img class="alignnone size-medium wp-image-299" title="ACE Awards" src="http://punechips.com/wp-content/uploads/2012/02/295620-2012_ACE_Awards-300x69.png" alt="Ace Awards" width="300" height="69" /></a><br />
Bangalore based startup, Saankhya Labs&#8217; Universal TV demodulator chip has been nominated as one of the finalists for the prestigious ACE awards instituted by UBM (publisher of EETimes and EDN) in the SoC category.</p>
<p><a href="http://punechips.com/saankhya-labs-nominated-for-eetimes-ace-awards/" [...]<br />
<p>Continue reading <a href="http://punechips.com/saankhya-labs-nominated-for-eetimes-ace-awards/">Saankhya Labs nominated for EETimes ACE Awards</a></p>]]></description>
			<content:encoded><![CDATA[<p><a href="http://punechips.com/wp-content/uploads/2012/02/295620-2012_ACE_Awards.png"><img class="alignnone size-medium wp-image-299" title="ACE Awards" src="http://punechips.com/wp-content/uploads/2012/02/295620-2012_ACE_Awards-300x69.png" alt="Ace Awards" width="300" height="69" /></a><br />
Bangalore based startup, Saankhya Labs&#8217; Universal TV demodulator chip has been nominated as one of the finalists for the prestigious ACE awards instituted by UBM (publisher of EETimes and EDN) in the SoC category.</p>
<p>Viewed in its rightful context, this is a major achievement. They are competing with Cadence, Calxeda, ST Micro and Xilinx. Please vote for them and create history.</p>
<p>Visit <a href="http://www.edn.com/info/2399-2012_ACE_Awards_Ultimate_Products.php" target="_blank">http://www.edn.com/info/2399-<wbr>2012_ACE_Awards_Ultimate_</wbr><wbr>Products.php</wbr></a> to vote.</p>
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		<title>Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</title>
		<link>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/</link>
		<comments>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/#comments</comments>
		<pubDate>Thu, 21 Jul 2011 10:48:56 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
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		<guid isPermaLink="false">http://punechips.com/?p=273</guid>
		<description><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/" [...]<br />
<p>Continue reading <a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/">Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</a></p>]]></description>
			<content:encoded><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a title="PCI Special Interest Group website" href="http://www.pcisig.com/specifications/pciexpress/" target="_blank">PCI Express</a> Architecture and Applications for FPGAs</p>
<p>Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards  to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI Express<sup>TM</sup>. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running Windows<sup>TM</sup>, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.</p>
<p><strong>About the speaker: <a title="Kiran Puranik Profile" href="http://www.linkedin.com/pub/kiran-puranik/4/945/647" target="_blank">Kiran Puranik</a></strong></p>
<p><strong></strong>Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.</p>
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		<title>Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business</title>
		<link>http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/</link>
		<comments>http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/#comments</comments>
		<pubDate>Mon, 11 Jul 2011 06:07:14 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
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		<description><![CDATA[<p><a title="LED Sign Board" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank"><img src="http://farm5.static.flickr.com/4051/4438502627_f11a21b9b7_m.jpg" border="0" alt="LED Sign Board" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="Patrick Hoesly" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank">Patrick Hoesly</a></small></p>
<p>Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.</p>
<h1>Click <a title="Building an Autonomous and Scalable Semiconductor VLSI Business" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank"><span style="color: #0000ff;">here </span></a>to download the PDF.</h1>
<p>This event is jointly brought to you by <a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips</a> and <a title="LSI Corporation" href="http://www.lsi.com" target="_blank">LSI Corporation</a>.</p>
<p><a href="http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/" [...]<br />
<p>Continue reading <a href="http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/">Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="LED Sign Board" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank"><img src="http://farm5.static.flickr.com/4051/4438502627_f11a21b9b7_m.jpg" border="0" alt="LED Sign Board" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="Patrick Hoesly" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank">Patrick Hoesly</a></small></p>
<p>Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.</p>
<h1>Click <a title="Building an Autonomous and Scalable Semiconductor VLSI Business" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank"><span style="color: #0000ff;">here </span></a>to download the PDF.</h1>
<p>This event is jointly brought to you by <a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips</a> and <a title="LSI Corporation" href="http://www.lsi.com" target="_blank">LSI Corporation</a>.</p>
<p>What: Technical Talk by Dr. T.R. Ramachandran on <a title="Building an Autonomous and Scalable Semiconductor VLSI Buisiness" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank">Building and Autonomoous and Scalable Semiconductor VLSI Business</a><br />
Where: Sargam Auditorium, 4th floor, <a title="LSI R&amp;D India Location" href="http://maps.google.com/maps?q=LSI+R%26D,+Pune,+Maharashtra,+India&amp;hl=en&amp;ll=18.56726,73.886919&amp;spn=0.02087,0.042272&amp;sll=33.097684,-116.999426&amp;sspn=0.036887,0.084543&amp;z=15" target="_blank">LSI India Research &amp; Development Private Limited</a>,  T +91 20 4010 4700<br />
When: Wednesday, July 13th 2011, 9:30am-11am. Please arrive by 9:00am for security registration and snack</p>
<p>RSVP: Reshma Arthani: <a href="mailto:Reshma.Artani@lsi.com" target="_blank"> Reshma.Artani@lsi.com</a>, Mobile: +91.992.320.3557</p>
<p>Abstract:</p>
<p>The presentation focuses on effective ways to build autonomous and scalable semiconductor VLSI businesses. The trends in the VLSI industry and inherent challenges of growth make autonomy &amp; scale-building essential elements of long-term success. This is particularly relevant to emerging geographies like India where there is increased focus on enhancing end-to-end capabilities and overall management.</p>
<p>About the <a title="T.R. Ramachandran LinkedIn Profile" href="http://www.linkedin.com/pub/t-r-ramachandran/4/60a/237" target="_blank">speaker</a>:</p>
<p>T. R. Ramachandran is Senior Director for Product Operations in the Storage Peripherals Division at LSI. In this role, he reports to the Senior Vice President and General Manager of the division and is responsible for the operations infrastructure, business processes, IP and customer program management across the entire product lifecycle from planning through manufacturing ramp for LSI’s highest volume semiconductor business. Before assuming this role, TR held a number of positions in LSI where he brought to bear a unique blend of expertise in a range of areas from business, operations &amp; program management, strategic/competitive analysis, large-scale M&amp;A and business transformations, global product development and deployment, and supplier &amp; manufacturing management. He lives in the United States in Northern California, and is keenly interested in various aspects of technology &amp; broader public policy as well as problems of scale tied to private, public and/or non-governmental sectors.</p>
<p>TR received a Bachelor’s degree in Metallurgical Engineering from IIT-M (Indian Institute of Technology in Madras/Chennai) and is a recipient of the Dr. Dhandapani Prize from IIT-M and the Vidya Bharati Prize conferred by the Indian Institute of Metals. He received his Masters and Ph.D. degrees in Materials Science from the University of Southern California, Los Angeles. His Ph.D. was focused on structural and optical studies of semiconductor thin films &amp; quantum dot nanostructures and innovative forays into nanotechnology using scanning probe microscopes.</p>
<p>&nbsp;</p>
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		<title>FPGA Virtual Summit is here again</title>
		<link>http://punechips.com/fpga-virtual-summit-is-here-again/</link>
		<comments>http://punechips.com/fpga-virtual-summit-is-here-again/#comments</comments>
		<pubDate>Wed, 01 Jun 2011 05:52:47 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Military]]></category>
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		<category><![CDATA[Video]]></category>
		<category><![CDATA[communications]]></category>
		<category><![CDATA[military]]></category>
		<category><![CDATA[video]]></category>
		<category><![CDATA[virtual conference]]></category>

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		<description><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&#38;eventid=309275&#38;sessionid=1&#38;key=A0209A9A7EF30D447CC09931B20BF03E&#38;partnerref=osmpromo1&#38;sourcepage=register " target="_blank">here </a>for registration.</p>
<p><a href="http://punechips.com/fpga-virtual-summit-is-here-again/" [...]<br />
<p>Continue reading <a href="http://punechips.com/fpga-virtual-summit-is-here-again/">FPGA Virtual Summit is here again</a></p>]]></description>
			<content:encoded><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&amp;eventid=309275&amp;sessionid=1&amp;key=A0209A9A7EF30D447CC09931B20BF03E&amp;partnerref=osmpromo1&amp;sourcepage=register " target="_blank">here </a>for registration.</p>
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		<title>Event: Digital Design and Prototyping with Verilog by Mr. Basu on April 28, 2011</title>
		<link>http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/</link>
		<comments>http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/#comments</comments>
		<pubDate>Tue, 19 Apr 2011 06:25:46 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[HDL]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[analog]]></category>
		<category><![CDATA[digital design]]></category>
		<category><![CDATA[mixed signal]]></category>
		<category><![CDATA[multicore]]></category>
		<category><![CDATA[prototyping]]></category>
		<category><![CDATA[simulation]]></category>
		<category><![CDATA[spice]]></category>
		<category><![CDATA[verilog]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=249</guid>
		<description><![CDATA[<p><a title="wafer - 5" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank"><img src="http://farm4.static.flickr.com/3420/3983788158_19fcd70ee7_m.jpg" border="0" alt="wafer - 5" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank">oskay</a></small></p>
<p>What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu<br />
When: April 28, 2011 from 9:00 am to 6:00 pm<br />
Where: ﻿Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008</p>
<p><a href="http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/" [...]<br />
<p>Continue reading <a href="http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/">Event: Digital Design and Prototyping with Verilog by Mr. Basu on April 28, 2011</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="wafer - 5" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank"><img src="http://farm4.static.flickr.com/3420/3983788158_19fcd70ee7_m.jpg" border="0" alt="wafer - 5" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank">oskay</a></small></p>
<p>What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu<br />
When: April 28, 2011 from 9:00 am to 6:00 pm<br />
Where: ﻿Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008</p>
<p>This event is not free. The fee is Rs. 1000 per person, which is hardly anything in our opinion. You can get a 25% discount if you bring your own laptop and a further 25% discount with a valid student ID. I want to encourage everyone interested to attend this seminar even though it is not free. Please call +91 20 2590 2984 to register. You can view the workshop details <a title="Digital Design with Verilog Flyer" href="http://www.venturecenter.co.in/workshops/pdfs/Digital-Design-Flyer_VC.pdf" target="_blank">here</a>.</p>
<p><strong>About the Speaker<br />
</strong>Mr Basu is a Design Engineer with experience in both Digital and Analog Design using a multitude of EDA and simulation tools. He has strong interests in Embedded systems design and multicore code design. He is a Hobby Robotics fan and entrepreneur in a related field. He has a B.Tech (H) &#8217;03  and  M.Tech &#8217;04  from Indian Institute Of Technology , Kharagpur.</p>
<p>He was the Component Design Engineer for Intel India&#8217;s first Multicore project where he also co-authored the Enhanced<br />
Structural Tester Based Functional Test methodology for Intel Multicore processors. He was also the Mixed-Signal Design<br />
Consultant for National Semiconductor&#8217;s Sponsored Project at IIT Kharagpur.</p>
<p>He is an accomplished researcher and speaker. A few of his research projects include:</p>
<ul>
<li>Behavioral Modelling for Mixed Signal Sytems using Verilog-AMS speeding up simulation times by 1000x</li>
<li>Analysis of spice simualtion engine for simulation speedup</li>
<li>Multi-core programming using Message Passing Interface and CUDA</li>
</ul>
<p>Previously, he has done similar seminars on Behavioral Modelling at IIT Kharagpur</p>
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		<title>Free Event: Advanced System Verilog Tips Including OVM &amp; UVM Tips by Cliff Cummings</title>
		<link>http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/</link>
		<comments>http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/#comments</comments>
		<pubDate>Sun, 10 Apr 2011 14:35:06 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[ASIC]]></category>
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		<category><![CDATA[pune]]></category>
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		<category><![CDATA[verification]]></category>
		<category><![CDATA['system verilog]]></category>
		<category><![CDATA[cadence]]></category>
		<category><![CDATA[cliff cummings. qlogic]]></category>
		<category><![CDATA[ovm]]></category>
		<category><![CDATA[uvm]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=243</guid>
		<description><![CDATA[<p><img src="http://www.sunburst-design.com/cliffc/photo_cliff_highres.gif" alt="Cliff Cummings photograph" height="320" align="left" /></p>
<p>SystemVerilog Guru <a title="Cliff Cummings Profile" href="http://www.sunburst-design.com/cliffc/" target="_blank">Cliff Cummings </a>is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit <a title="SystemVerilog Seminar Invite" href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=530" target="_blank">this</a> link to register and view the agenda.</p>
<p><a href="http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/" [...]<br />
<p>Continue reading <a href="http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/">Free Event: Advanced System Verilog Tips Including OVM &#038; UVM Tips by Cliff Cummings</a></p>]]></description>
			<content:encoded><![CDATA[<p><img src="http://www.sunburst-design.com/cliffc/photo_cliff_highres.gif" alt="Cliff Cummings photograph" height="320" align="left" /></p>
<p>SystemVerilog Guru <a title="Cliff Cummings Profile" href="http://www.sunburst-design.com/cliffc/" target="_blank">Cliff Cummings </a>is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit <a title="SystemVerilog Seminar Invite" href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=530" target="_blank">this</a> link to register and view the agenda.</p>
<p> This event is co-sponsored by <a title="QLogic" href="http://www.qlogic.com/Pages/default.aspx" target="_blank">Qlogic </a>and <a title="Cadence India" href="http://www.cadence.com/in/pages/default.aspx" target="_blank">Cadence </a>who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.</p>
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		<title>Mobile Networks &#8211; Moving from 3G to 4G</title>
		<link>http://punechips.com/mobile-networks-moving-from-3g-to-4g/</link>
		<comments>http://punechips.com/mobile-networks-moving-from-3g-to-4g/#comments</comments>
		<pubDate>Thu, 24 Feb 2011 07:22:42 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[event]]></category>
		<category><![CDATA[featured]]></category>
		<category><![CDATA[mobile]]></category>
		<category><![CDATA[pune]]></category>
		<category><![CDATA[Telecom]]></category>
		<category><![CDATA[Wireless]]></category>
		<category><![CDATA[2.5G]]></category>
		<category><![CDATA[3G]]></category>
		<category><![CDATA[4G]]></category>
		<category><![CDATA[CDMA]]></category>
		<category><![CDATA[GPRS]]></category>
		<category><![CDATA[GSM]]></category>
		<category><![CDATA[LTE]]></category>
		<category><![CDATA[UMTS]]></category>
		<category><![CDATA[WiMAX]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=222</guid>
		<description><![CDATA[<p><a title="4G ad (80 Mbit)" href="http://www.flickr.com/photos/82365211@N00/5233599415/" target="_blank"><img src="http://farm6.static.flickr.com/5287/5233599415_5211575266_m.jpg" border="0" alt="4G ad (80 Mbit)" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="kalleboo" href="http://www.flickr.com/photos/82365211@N00/5233599415/" target="_blank">kalleboo</a></small></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: Talk by Gandhar Gokhale on Moving from <a title="3G" href="http://en.wikipedia.org/wiki/3G" target="_blank">3G </a>to <a title="4G" href="http://en.wikipedia.org/wiki/4G" target="_blank">4G</a><br />
When: Saturday, 26th March 2011, 10:30 am to 12:00 noon.<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, Classroom E, NCL Innovation Park, Pashan Road</p>
<p><a href="http://punechips.com/mobile-networks-moving-from-3g-to-4g/" [...]<br />
<p>Continue reading <a href="http://punechips.com/mobile-networks-moving-from-3g-to-4g/">Mobile Networks &#8211; Moving from 3G to 4G</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="4G ad (80 Mbit)" href="http://www.flickr.com/photos/82365211@N00/5233599415/" target="_blank"><img src="http://farm6.static.flickr.com/5287/5233599415_5211575266_m.jpg" border="0" alt="4G ad (80 Mbit)" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="kalleboo" href="http://www.flickr.com/photos/82365211@N00/5233599415/" target="_blank">kalleboo</a></small></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: Talk by Gandhar Gokhale on Moving from <a title="3G" href="http://en.wikipedia.org/wiki/3G" target="_blank">3G </a>to <a title="4G" href="http://en.wikipedia.org/wiki/4G" target="_blank">4G</a><br />
When: Saturday, 26th March 2011, 10:30 am to 12:00 noon.<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, Classroom E, NCL Innovation Park, Pashan Road</p>
<p>Registration and fees: This event is *FREE* for all to attend. No registration required.</p>
<p><strong><a title="Mobile Networks" href="http://en.wikipedia.org/wiki/Mobile_network" target="_blank">Mobile Networks </a>- Moving from 3G to 4G<br />
</strong>This presentation will be an introduction to the mobile network evolution. It&#8217;ll run through the evolution of generations of mobile networks to the upcoming 4G.  The radio interface and terrestrial network evolution in each generation will be briefly touched upon. The <a title="LTE" href="http://en.wikipedia.org/wiki/Long_Term_Evolution" target="_blank">LTE </a>(Long Term Evolution) as the candidate technology for 4G shall be explored. We&#8217;ll conclude by discussing how these generations have impacted or shall impact our lives.</p>
<p><strong>About the Speaker &#8211; Gandhar Gokhale<br />
</strong>Gandhar Gokhale is a software architech with LSI Corporation. He has more than 12 years of Network Software development and Network Security experience. He completed his  M.E. (Telecom) from IISc Bangalore and B.E. (Electronics) from WCE Sangli.</p>
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		<title>Event: Storage and Networking Protocols for the Next Generation</title>
		<link>http://punechips.com/storage-and-networking-protocol/</link>
		<comments>http://punechips.com/storage-and-networking-protocol/#comments</comments>
		<pubDate>Tue, 05 Oct 2010 17:06:35 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[event]]></category>
		<category><![CDATA[Networking]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Storage]]></category>
		<category><![CDATA[technology]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=183</guid>
		<description><![CDATA[<div id="attachment_184" class="wp-caption alignnone" style="width: 743px"><a href="http://punechips.com/wp-content/uploads/2010/10/image001.jpg"><img class="size-large wp-image-184 " title="Flier: Howard Goldstein's lecture for PuneChips" src="http://punechips.com/wp-content/uploads/2010/10/image001-733x1024.jpg" alt="Flier: Howard Goldstein's lecture for PuneChips" width="733" height="1024" /></a><p class="wp-caption-text">PuneChips Event: Storage and Networking Protocols for the next generation</p></div>
<p>This is a PuneChips event</p>
<p>What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein<br />
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune<br />
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)</p>
<p><a href="http://punechips.com/storage-and-networking-protocol/" [...]<br />
<p>Continue reading <a href="http://punechips.com/storage-and-networking-protocol/">Event: Storage and Networking Protocols for the Next Generation</a></p>]]></description>
			<content:encoded><![CDATA[<div id="attachment_184" class="wp-caption alignnone" style="width: 743px"><a href="http://punechips.com/wp-content/uploads/2010/10/image001.jpg"><img class="size-large wp-image-184 " title="Flier: Howard Goldstein's lecture for PuneChips" src="http://punechips.com/wp-content/uploads/2010/10/image001-733x1024.jpg" alt="Flier: Howard Goldstein's lecture for PuneChips" width="733" height="1024" /></a><p class="wp-caption-text">PuneChips Event: Storage and Networking Protocols for the next generation</p></div>
<p>This is a PuneChips event</p>
<p>What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein<br />
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune<br />
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)</p>
<p>Registration and Fees: This is a <strong>FREE</strong> event. Seating is limited. To attend, please RSVP: <a href="mailto:sulekha.thakkar@qlogic.com" target="_blank">sulekha.thakkar@qlogic.com</a>.</p>
<div id="_mcePaste">For more details on Howard&#8217;s talk, please see the attached flier.</div>
<div id="_mcePaste">This event is sponsored by <a title="QLogic" href="http://www.qlogic.com" target="_blank">QLogic</a>, a global leader and technology innovator in high performance networking, and supported by <a title="ISA" href="http://www.isaonline.org" target="_blank">ISA </a>(Indian Semiconductor Association), the premier trade body Indian Electronic System Design and Manufacturing Industry.</div>
<div></div>
<div id="_mcePaste"><a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips </a>is the forum for semiconductor, EDA and applications designers in and around Pune. It was formed to foster an environment for the growth of semiconductor, EDA and applications companies in and around Pune. For more details, visit our website at www.punechips.com. If you wish to contribute to the community, please join the PuneChips group on groups.google.com. You can also join the PuneChips group on LinkedIn.</div>
<div></div>
<div id="_mcePaste">Please forward this e-mail to anyone in Pune interested in semiconductors, chip design and verification, VLSI design, and embedded design.</div>
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