Nvidia Tech Week Open House

By punechips

I was invited to visit the Nvidia Tech Week this past weekend (February 25-26, 2012) at their facilities in Pune. This is a great concept – getting employees to invite friends and relatives to actually see what their company is all about is very good social outreach and a fantastic marketing initiative. If more tech companies in the area do similar events once or twice a year, it will help lift the shroud of technical opaqueness around them. I think hosting similar events in area colleges will also help students realize that even VLSI/Embedded Systems Design is cool.

Continue reading Nvidia Tech Week Open House – February 25/26, 2012

Saankhya Labs nominated for EETimes ACE Awards

By punechips

Bangalore based startup, Saankhya Labs’ Universal TV demodulator chip has been nominated as one of the finalists for the prestigious ACE awards instituted by UBM (publisher of EETimes and EDN) in the SoC category.

Continue reading Saankhya Labs nominated for EETimes ACE Awards

Korea as a Memory Hub and India as a ... ?

By punechips

Semiconductor Manufacturing Plant

I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how Korea became the De-facto memory hub. The story of Korea in the 1960s and where India is now is uncannily similar. Hopefully, the Indian Government takes lessons from this and formulates a policy that works here. Let’s look at the points Deepak makes and see what could be applicable in the Indian context:

Continue reading Korea as a Memory Hub and India as a … ?

PCI Express Architecture and Applications for FPGAs by Kiran Puranik

By punechips

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik
When: July 30, 2011 from 10:30 am to 12:00 noon
Where: Venture Center, NCL Innovation Park, Pashan Road

Continue reading Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik

Building an Autonomous and Scalable Semiconductor VLSI Business by Dr. T.R. Ramachandran

By punechips

photo credit: Patrick Hoesly

Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.

Click here to download the PDF.

This event is jointly brought to you by PuneChips and LSI Corporation.

Continue reading Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business

Mobile Networks - Moving from 3G to 4G

By punechips

photo credit: kalleboo

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Gandhar Gokhale on Moving from 3G to 4G
When: Saturday, 26th March 2011, 10:30 am to 12:00 noon.
Where: Venture Center, Classroom E, NCL Innovation Park, Pashan Road

Continue reading Mobile Networks – Moving from 3G to 4G

Cadence Acquires Taray

By punechips

FPGA as the PCB's Grand Central Station

Earlier this week, Cadence Design Systems acquired an EDA startup, Taray, Inc. Financial terms were not disclosed.

This is important because it is an Indian EDA product company story. While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.

Continue reading Cadence Acquires Taray

Introduction to Chip Verification Planning

By punechips

This is the first in a series of blogs written for PuneChips by Suhas Belgal titled Field Manual for Verification Planning. The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.

Continue reading Introduction to Chip Verification Planning

How Green will be My Valley?

By punechips

(This is a guest blog by Chaitanya Rajguru, Associate Technical Fellow at KPIT Cummins, and a member of the PuneChips group.)

The “greening” of all things commercial and industrial is all around us. Every industry from transportation to technology to power to finance is in a rush to be perceived as “green”. So should the EDA industry stay behind? I think not. And here are my thoughts on some possible scenarios on what may happen.

So where does one begin? One good starting point may be with a popular indicator used to gauge the “goodness” of EDA tool’s output: “Quality of Results”, or QoR. QoR is used as a higher-level indicator of process quality, much like a Customer Satisfaction Index that up-levels feedback on specific aspects such as timely delivery and responsiveness. IC design EDA tools have used to showcase what they can do. So is it possible to expand its scope to include “greenness” as well? Or is it just an attempt to paint a turkey blue and pass it off as a peacock?

Continue reading How Green will be My Valley?

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Nvidia Tech Week Open House

Saankhya Labs nominated for EETimes ACE Awards

Korea as a Memory Hub and India as a ... ?

PCI Express Architecture and Applications for FPGAs by Kiran Puranik

Building an Autonomous and Scalable Semiconductor VLSI Business by Dr. T.R. Ramachandran

Click here to download the PDF.

Mobile Networks - Moving from 3G to 4G

Cadence Acquires Taray

Introduction to Chip Verification Planning

How Green will be My Valley?

PuneChips Calendar

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