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	<title>Pune&#039;s Semi/EDA &#38; Embedded Forum &#187; semiconductor</title>
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	<description>Pune&#039;s Forum for Semiconductor/EDA and Embedded Design</description>
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		<title>Korea as a Memory Hub and India as a &#8230; ?</title>
		<link>http://punechips.com/korea-as-a-memory-hub-and-india-as-a/</link>
		<comments>http://punechips.com/korea-as-a-memory-hub-and-india-as-a/#comments</comments>
		<pubDate>Fri, 25 Nov 2011 10:15:31 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[featured]]></category>
		<category><![CDATA[India]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[VLSI]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=281</guid>
		<description><![CDATA[<div id="attachment_287" class="wp-caption alignnone" style="width: 310px"><a href="http://punechips.com/wp-content/uploads/2011/11/intro-fab.jpg"><img class="size-medium wp-image-287" title="Semiconductor Manufacturing: Source - Tom's Hardware" src="http://punechips.com/wp-content/uploads/2011/11/intro-fab-300x240.jpg" alt="Semiconductor Manufacturing" width="300" height="240" /></a><p class="wp-caption-text">Semiconductor Manufacturing Plant</p></div>
<p>I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how <a title="How Korea became the Memory Hub of the World" href="http://www.linkedin.com/news?viewArticle=&#38;articleID=927413462&#38;gid=1795490&#38;type=member&#38;item=81399303&#38;articleURL=http%3A%2F%2Fwww.monolithic3d.com%2F2%2Fpost%2F2011%2F11%2Fhow-korea-became-the-hub-of-the-memory-industry.html&#38;urlhash=zl5P&#38;goback=.gde_1795490_member_81399303" target="_blank">Korea became the De-facto memory hub</a>. The story of Korea in the 1960s and where India is now is uncannily similar. Hopefully, the Indian Government takes lessons from this and formulates a policy that works here. Let&#8217;s look at the points Deepak makes and see what could be applicable in the Indian context:</p>
<p><a href="http://punechips.com/korea-as-a-memory-hub-and-india-as-a/" [...]<br />
<p>Continue reading <a href="http://punechips.com/korea-as-a-memory-hub-and-india-as-a/">Korea as a Memory Hub and India as a &#8230; ?</a></p>]]></description>
			<content:encoded><![CDATA[<div id="attachment_287" class="wp-caption alignnone" style="width: 310px"><a href="http://punechips.com/wp-content/uploads/2011/11/intro-fab.jpg"><img class="size-medium wp-image-287" title="Semiconductor Manufacturing: Source - Tom's Hardware" src="http://punechips.com/wp-content/uploads/2011/11/intro-fab-300x240.jpg" alt="Semiconductor Manufacturing" width="300" height="240" /></a><p class="wp-caption-text">Semiconductor Manufacturing Plant</p></div>
<p>I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how <a title="How Korea became the Memory Hub of the World" href="http://www.linkedin.com/news?viewArticle=&amp;articleID=927413462&amp;gid=1795490&amp;type=member&amp;item=81399303&amp;articleURL=http%3A%2F%2Fwww.monolithic3d.com%2F2%2Fpost%2F2011%2F11%2Fhow-korea-became-the-hub-of-the-memory-industry.html&amp;urlhash=zl5P&amp;goback=.gde_1795490_member_81399303" target="_blank">Korea became the De-facto memory hub</a>. The story of Korea in the 1960s and where India is now is uncannily similar. Hopefully, the Indian Government takes lessons from this and formulates a policy that works here. Let&#8217;s look at the points Deepak makes and see what could be applicable in the Indian context:</p>
<h3>Agrarian Economy</h3>
<p>Like Korea in the 1960s, India today is primarily an agrarian economy, in the sense that a majority (70%+) of its populations lives in villages performing farming or related occupations. As the government is tries to move the teeming masses to higher paying occupations, a focused policy to dominate in particular semiconductor manufacturing segments might just be the ticket. Like Korea did it with memories, India could focus on 3D chips or microprocessors or DSPs.</p>
<h3>Chaebols and Access to Capital</h3>
<p>Chaebols are classical Korean conglomerates often owned by a single family. All old school major Indian businesses have a similar structure &#8211; Tata, Birla, Reliance, Mahindra, Videocon to name a few. These business groups for the longest time have been using funds from successful groups companies to start new ventures. It is not inconceivable that they could be goaded or cajoled to start semiconductor manufacturing in a huge way. In fact, Reliance was to enter the Semiconductor manufacturing space, but the plans were shelved after the crash of 2008. If the Indian government as a matter of policy actually gives easy access to capital for forming semiconductor businesses, these Indian Chaebols could step up to the plate and take on the challenge. They certainly have done similar things in the past and this would be no different.</p>
<h3>New Technologies</h3>
<p>Starting a manufacturing business from scratch requires that you look at brand new cutting edge technologies without any of the baggage of the past. You don&#8217;t have to worry whether a legacy technology could be migrated to the new line. Newer technologies with a clean start can allow Indian semiconductor manufacturers to leapfrog external competition that must worry about process node transition and migration. If executed properly, India can take a huge lead in a particular semiconductor space.</p>
<h3>Low Cost Manufacturing Location</h3>
<p>India is still far cheaper compared to the US, the EU, Japan and even China. Additionally, it has a deep pool of resources who actually know how semiconductors are built. This is an inherent advantage that Korea did not have in the 1960s when they only had lower cost.</p>
<p>In fact, all the ingredients for a perfect storm, low costs, talent, land, capital availability and successful business houses are present. All it needs is policy implementation. Of course, this blog and many others can talk ad nauseam about the Indian semiconductor policy. The question is whether the governments, state of central, act and help bring visions into reality.</p>
<p>&nbsp;</p>
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		<title>Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</title>
		<link>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/</link>
		<comments>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/#comments</comments>
		<pubDate>Thu, 21 Jul 2011 10:48:56 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[featured]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Serial IO]]></category>
		<category><![CDATA[PCI Express]]></category>
		<category><![CDATA[serial IO]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=273</guid>
		<description><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/" [...]<br />
<p>Continue reading <a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/">Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</a></p>]]></description>
			<content:encoded><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a title="PCI Special Interest Group website" href="http://www.pcisig.com/specifications/pciexpress/" target="_blank">PCI Express</a> Architecture and Applications for FPGAs</p>
<p>Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards  to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI Express<sup>TM</sup>. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running Windows<sup>TM</sup>, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.</p>
<p><strong>About the speaker: <a title="Kiran Puranik Profile" href="http://www.linkedin.com/pub/kiran-puranik/4/945/647" target="_blank">Kiran Puranik</a></strong></p>
<p><strong></strong>Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.</p>
]]></content:encoded>
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		<title>Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business</title>
		<link>http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/</link>
		<comments>http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/#comments</comments>
		<pubDate>Mon, 11 Jul 2011 06:07:14 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[ASIC]]></category>
		<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[event report]]></category>
		<category><![CDATA[featured]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[VLSI]]></category>
		<category><![CDATA[business]]></category>
		<category><![CDATA[LSI]]></category>
		<category><![CDATA[pune]]></category>
		<category><![CDATA[punechips]]></category>
		<category><![CDATA[T.R.Ramachandran]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=260</guid>
		<description><![CDATA[<p><a title="LED Sign Board" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank"><img src="http://farm5.static.flickr.com/4051/4438502627_f11a21b9b7_m.jpg" border="0" alt="LED Sign Board" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="Patrick Hoesly" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank">Patrick Hoesly</a></small></p>
<p>Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.</p>
<h1>Click <a title="Building an Autonomous and Scalable Semiconductor VLSI Business" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank"><span style="color: #0000ff;">here </span></a>to download the PDF.</h1>
<p>This event is jointly brought to you by <a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips</a> and <a title="LSI Corporation" href="http://www.lsi.com" target="_blank">LSI Corporation</a>.</p>
<p><a href="http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/" [...]<br />
<p>Continue reading <a href="http://punechips.com/building-an-autonomous-and-scalable-semiconductor-vlsi-business-by-dr-t-r-ramachandran/">Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="LED Sign Board" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank"><img src="http://farm5.static.flickr.com/4051/4438502627_f11a21b9b7_m.jpg" border="0" alt="LED Sign Board" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="Patrick Hoesly" href="http://www.flickr.com/photos/60057912@N00/4438502627/" target="_blank">Patrick Hoesly</a></small></p>
<p>Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.</p>
<h1>Click <a title="Building an Autonomous and Scalable Semiconductor VLSI Business" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank"><span style="color: #0000ff;">here </span></a>to download the PDF.</h1>
<p>This event is jointly brought to you by <a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips</a> and <a title="LSI Corporation" href="http://www.lsi.com" target="_blank">LSI Corporation</a>.</p>
<p>What: Technical Talk by Dr. T.R. Ramachandran on <a title="Building an Autonomous and Scalable Semiconductor VLSI Buisiness" href="http://www.eng.ucy.ac.cy/theocharides/isvlsi11/ISVLSI2011_TR_vFINAL.pdf" target="_blank">Building and Autonomoous and Scalable Semiconductor VLSI Business</a><br />
Where: Sargam Auditorium, 4th floor, <a title="LSI R&amp;D India Location" href="http://maps.google.com/maps?q=LSI+R%26D,+Pune,+Maharashtra,+India&amp;hl=en&amp;ll=18.56726,73.886919&amp;spn=0.02087,0.042272&amp;sll=33.097684,-116.999426&amp;sspn=0.036887,0.084543&amp;z=15" target="_blank">LSI India Research &amp; Development Private Limited</a>,  T +91 20 4010 4700<br />
When: Wednesday, July 13th 2011, 9:30am-11am. Please arrive by 9:00am for security registration and snack</p>
<p>RSVP: Reshma Arthani: <a href="mailto:Reshma.Artani@lsi.com" target="_blank"> Reshma.Artani@lsi.com</a>, Mobile: +91.992.320.3557</p>
<p>Abstract:</p>
<p>The presentation focuses on effective ways to build autonomous and scalable semiconductor VLSI businesses. The trends in the VLSI industry and inherent challenges of growth make autonomy &amp; scale-building essential elements of long-term success. This is particularly relevant to emerging geographies like India where there is increased focus on enhancing end-to-end capabilities and overall management.</p>
<p>About the <a title="T.R. Ramachandran LinkedIn Profile" href="http://www.linkedin.com/pub/t-r-ramachandran/4/60a/237" target="_blank">speaker</a>:</p>
<p>T. R. Ramachandran is Senior Director for Product Operations in the Storage Peripherals Division at LSI. In this role, he reports to the Senior Vice President and General Manager of the division and is responsible for the operations infrastructure, business processes, IP and customer program management across the entire product lifecycle from planning through manufacturing ramp for LSI’s highest volume semiconductor business. Before assuming this role, TR held a number of positions in LSI where he brought to bear a unique blend of expertise in a range of areas from business, operations &amp; program management, strategic/competitive analysis, large-scale M&amp;A and business transformations, global product development and deployment, and supplier &amp; manufacturing management. He lives in the United States in Northern California, and is keenly interested in various aspects of technology &amp; broader public policy as well as problems of scale tied to private, public and/or non-governmental sectors.</p>
<p>TR received a Bachelor’s degree in Metallurgical Engineering from IIT-M (Indian Institute of Technology in Madras/Chennai) and is a recipient of the Dr. Dhandapani Prize from IIT-M and the Vidya Bharati Prize conferred by the Indian Institute of Metals. He received his Masters and Ph.D. degrees in Materials Science from the University of Southern California, Los Angeles. His Ph.D. was focused on structural and optical studies of semiconductor thin films &amp; quantum dot nanostructures and innovative forays into nanotechnology using scanning probe microscopes.</p>
<p>&nbsp;</p>
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		<title>FPGA Virtual Summit is here again</title>
		<link>http://punechips.com/fpga-virtual-summit-is-here-again/</link>
		<comments>http://punechips.com/fpga-virtual-summit-is-here-again/#comments</comments>
		<pubDate>Wed, 01 Jun 2011 05:52:47 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Military]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Telecom]]></category>
		<category><![CDATA[Video]]></category>
		<category><![CDATA[communications]]></category>
		<category><![CDATA[military]]></category>
		<category><![CDATA[video]]></category>
		<category><![CDATA[virtual conference]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=248</guid>
		<description><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&#38;eventid=309275&#38;sessionid=1&#38;key=A0209A9A7EF30D447CC09931B20BF03E&#38;partnerref=osmpromo1&#38;sourcepage=register " target="_blank">here </a>for registration.</p>
<p><a href="http://punechips.com/fpga-virtual-summit-is-here-again/" [...]<br />
<p>Continue reading <a href="http://punechips.com/fpga-virtual-summit-is-here-again/">FPGA Virtual Summit is here again</a></p>]]></description>
			<content:encoded><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&amp;eventid=309275&amp;sessionid=1&amp;key=A0209A9A7EF30D447CC09931B20BF03E&amp;partnerref=osmpromo1&amp;sourcepage=register " target="_blank">here </a>for registration.</p>
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		<title>Event: Digital Design and Prototyping with Verilog by Mr. Basu on April 28, 2011</title>
		<link>http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/</link>
		<comments>http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/#comments</comments>
		<pubDate>Tue, 19 Apr 2011 06:25:46 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[HDL]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[analog]]></category>
		<category><![CDATA[digital design]]></category>
		<category><![CDATA[mixed signal]]></category>
		<category><![CDATA[multicore]]></category>
		<category><![CDATA[prototyping]]></category>
		<category><![CDATA[simulation]]></category>
		<category><![CDATA[spice]]></category>
		<category><![CDATA[verilog]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=249</guid>
		<description><![CDATA[<p><a title="wafer - 5" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank"><img src="http://farm4.static.flickr.com/3420/3983788158_19fcd70ee7_m.jpg" border="0" alt="wafer - 5" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank">oskay</a></small></p>
<p>What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu<br />
When: April 28, 2011 from 9:00 am to 6:00 pm<br />
Where: ﻿Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008</p>
<p><a href="http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/" [...]<br />
<p>Continue reading <a href="http://punechips.com/event-digital-design-and-prototyping-with-verilog-by-mr-basu-on-april-28-2011/">Event: Digital Design and Prototyping with Verilog by Mr. Basu on April 28, 2011</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="wafer - 5" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank"><img src="http://farm4.static.flickr.com/3420/3983788158_19fcd70ee7_m.jpg" border="0" alt="wafer - 5" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983788158/" target="_blank">oskay</a></small></p>
<p>What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu<br />
When: April 28, 2011 from 9:00 am to 6:00 pm<br />
Where: ﻿Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008</p>
<p>This event is not free. The fee is Rs. 1000 per person, which is hardly anything in our opinion. You can get a 25% discount if you bring your own laptop and a further 25% discount with a valid student ID. I want to encourage everyone interested to attend this seminar even though it is not free. Please call +91 20 2590 2984 to register. You can view the workshop details <a title="Digital Design with Verilog Flyer" href="http://www.venturecenter.co.in/workshops/pdfs/Digital-Design-Flyer_VC.pdf" target="_blank">here</a>.</p>
<p><strong>About the Speaker<br />
</strong>Mr Basu is a Design Engineer with experience in both Digital and Analog Design using a multitude of EDA and simulation tools. He has strong interests in Embedded systems design and multicore code design. He is a Hobby Robotics fan and entrepreneur in a related field. He has a B.Tech (H) &#8217;03  and  M.Tech &#8217;04  from Indian Institute Of Technology , Kharagpur.</p>
<p>He was the Component Design Engineer for Intel India&#8217;s first Multicore project where he also co-authored the Enhanced<br />
Structural Tester Based Functional Test methodology for Intel Multicore processors. He was also the Mixed-Signal Design<br />
Consultant for National Semiconductor&#8217;s Sponsored Project at IIT Kharagpur.</p>
<p>He is an accomplished researcher and speaker. A few of his research projects include:</p>
<ul>
<li>Behavioral Modelling for Mixed Signal Sytems using Verilog-AMS speeding up simulation times by 1000x</li>
<li>Analysis of spice simualtion engine for simulation speedup</li>
<li>Multi-core programming using Message Passing Interface and CUDA</li>
</ul>
<p>Previously, he has done similar seminars on Behavioral Modelling at IIT Kharagpur</p>
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		<title>Free Event: Advanced System Verilog Tips Including OVM &amp; UVM Tips by Cliff Cummings</title>
		<link>http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/</link>
		<comments>http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/#comments</comments>
		<pubDate>Sun, 10 Apr 2011 14:35:06 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[ASIC]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[pune]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[verification]]></category>
		<category><![CDATA['system verilog]]></category>
		<category><![CDATA[cadence]]></category>
		<category><![CDATA[cliff cummings. qlogic]]></category>
		<category><![CDATA[ovm]]></category>
		<category><![CDATA[uvm]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=243</guid>
		<description><![CDATA[<p><img src="http://www.sunburst-design.com/cliffc/photo_cliff_highres.gif" alt="Cliff Cummings photograph" height="320" align="left" /></p>
<p>SystemVerilog Guru <a title="Cliff Cummings Profile" href="http://www.sunburst-design.com/cliffc/" target="_blank">Cliff Cummings </a>is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit <a title="SystemVerilog Seminar Invite" href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=530" target="_blank">this</a> link to register and view the agenda.</p>
<p><a href="http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/" [...]<br />
<p>Continue reading <a href="http://punechips.com/free-event-advanced-system-verilog-tips-including-ovm-uvm-tips-by-cliff-cummings/">Free Event: Advanced System Verilog Tips Including OVM &#038; UVM Tips by Cliff Cummings</a></p>]]></description>
			<content:encoded><![CDATA[<p><img src="http://www.sunburst-design.com/cliffc/photo_cliff_highres.gif" alt="Cliff Cummings photograph" height="320" align="left" /></p>
<p>SystemVerilog Guru <a title="Cliff Cummings Profile" href="http://www.sunburst-design.com/cliffc/" target="_blank">Cliff Cummings </a>is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit <a title="SystemVerilog Seminar Invite" href="http://www.cadence.com/cadence/events/Pages/event.aspx?eventid=530" target="_blank">this</a> link to register and view the agenda.</p>
<p> This event is co-sponsored by <a title="QLogic" href="http://www.qlogic.com/Pages/default.aspx" target="_blank">Qlogic </a>and <a title="Cadence India" href="http://www.cadence.com/in/pages/default.aspx" target="_blank">Cadence </a>who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.</p>
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		<title>India Needs Angels, not Fabs to Propel Semiconductor Growth</title>
		<link>http://punechips.com/india-needs-angels-not-subsidies-to-propel-semiconductor-growth/</link>
		<comments>http://punechips.com/india-needs-angels-not-subsidies-to-propel-semiconductor-growth/#comments</comments>
		<pubDate>Fri, 10 Dec 2010 11:50:07 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[India]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[angel]]></category>
		<category><![CDATA[fab]]></category>
		<category><![CDATA[fabless]]></category>
		<category><![CDATA[VC]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=202</guid>
		<description><![CDATA[<p><a title="Pentium-4/3.0GHz" href="http://www.flickr.com/photos/63794141@N00/4536472550/" target="_blank"><img src="http://farm3.static.flickr.com/2690/4536472550_abcb062cb0_m.jpg" border="0" alt="Pentium-4/3.0GHz" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="yellowcloud" href="http://www.flickr.com/photos/63794141@N00/4536472550/" target="_blank">yellowcloud</a></small></p>
<p>It has been well over twenty five years since Texas Instruments first set up shop in Bangalore. Other global semiconductor vendors have since made Bangalore, and more recently NOIDA, Hyderabad, Pune and Chennai into huge R&#38;D hubs that develop products for global consumption. Indian engineers are now designing latest chips and systems using cutting edge technologies.  However, not a single Indian chip company has emerged onto the global scene given all this teeming talent. This in itself is surprising, as the low cost Indian environment should make hi-tech businesses thrive. It is said that a semiconductor startup in the Silicon Valley has to raise funds in the range of of US $50m &#8211; $60m to be successful. With India&#8217;s lower costs of engineering resources, this number could be cut by half or a third, and make life much more simple for the VC as well as the entrepreneur. However, we don&#8217;t really see this happening. Why? Probably because India lacks the advanced angel investor culture that focusses on funding and advising hi-technology startups.</p>
<p><a href="http://punechips.com/india-needs-angels-not-subsidies-to-propel-semiconductor-growth/" [...]<br />
<p>Continue reading <a href="http://punechips.com/india-needs-angels-not-subsidies-to-propel-semiconductor-growth/">India Needs Angels, not Fabs to Propel Semiconductor Growth</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="Pentium-4/3.0GHz" href="http://www.flickr.com/photos/63794141@N00/4536472550/" target="_blank"><img src="http://farm3.static.flickr.com/2690/4536472550_abcb062cb0_m.jpg" border="0" alt="Pentium-4/3.0GHz" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absMiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="yellowcloud" href="http://www.flickr.com/photos/63794141@N00/4536472550/" target="_blank">yellowcloud</a></small></p>
<p>It has been well over twenty five years since Texas Instruments first set up shop in Bangalore. Other global semiconductor vendors have since made Bangalore, and more recently NOIDA, Hyderabad, Pune and Chennai into huge R&amp;D hubs that develop products for global consumption. Indian engineers are now designing latest chips and systems using cutting edge technologies.  However, not a single Indian chip company has emerged onto the global scene given all this teeming talent. This in itself is surprising, as the low cost Indian environment should make hi-tech businesses thrive. It is said that a semiconductor startup in the Silicon Valley has to raise funds in the range of of US $50m &#8211; $60m to be successful. With India&#8217;s lower costs of engineering resources, this number could be cut by half or a third, and make life much more simple for the VC as well as the entrepreneur. However, we don&#8217;t really see this happening. Why? Probably because India lacks the advanced angel investor culture that focusses on funding and advising hi-technology startups.</p>
<p>In this day and age, it is practically impossible to bootstrap a semiconductor startup unless you are Bill Gates. Most startups require funding once they exhaust funds raised from friends, family and founders and it is very early at this stage for venture capitalists who typically do not invest less than $1m. Angel investors typically fill the gap between the friends and family funds and VC funds. It is estimated that in the US, between 300K to 600K angels invest $40B in over 5000 companies per year. However, the risk associated with an angel round is very high and they lose the money outright in many cases. In order to normalize this, they look for investing in companies that have the potential to offer 10x return on investment. Sadly, India does not have a culture of angel investments yet, maybe because the hi-tech industry is immature and there have not been too many successful hi-tech entrepreneurs. It takes one to know one. A few networks exist, but their exposure to hi-tech is very limited. Most invest in businesses they understand.</p>
<p>How do we change this? There is no easy answer, but Indian government resources would be better served towards the creation of an angel fund that exclusively invests in hi-tech rather than dishing out subsidies to build semiconductor fabrication houses (&#8216;fabs&#8217;). Fabs are good and they bring jobs, but they are not the best option to build wealth in a coutry like India, where the principle reason for getting fabs seems to be because China has got&#8217;em. Creating semiconductor startups that build products using the fabless model, where they actually outsource all manufacturing to an external fab, will build more wealth and have a much greater impact on the Indian GDP. There was a time when every semiconductor company in the world had to have a fab. But not anymore; there are about 200 integrated device manufacturers, 1500 fabless companies and 125 fabs in the world today.<a href="http://www.gsaglobal.org/resources/industrydata/facts.asp" target="_blank"> This page </a>has some excellent data.</p>
<p>Let&#8217;s look at this in a bit more detail. Of those 125 fabs, only the top twelve or so really earn significant revenues. Even among those, the top 4 &#8211; TSMC, UMC, SMIC and Global Foundries make 90% of revenue. In all likelihood, they service 90% of all fabless semiconductor companies. Looking at market caps for these 4 fabs, TSMC has a market cap of $62B, UMC $8B, and SMIC $2B. Global foundries is private so the market cap is unknown, but not likely to be more than UMC&#8217;s. Compared to this, of the 1500 or so fabless companies, the top 100 companies have revenues much greater than all the fabs in the world, the valuation is far greater than all the fabs in the world. In addition, a fabless semiconductor company can be started and possibly made successful with $50m investment even in the Valley and much lesser in India. By contrast, a 65nm fab requires at least $3B investment and additional subsidies and consumes far more natural resources. It absolutely does not make sense to encourage building fabs at the expense of promoting and nurturing semiconductor startups.</p>
<p>If the $40B or so supposedly lost in the telecom scam were turned into an angel fund, 8000 companies can each get $500K as their angel round. Using a 1% success rate, even if 80 companies make a successful exit, the exercise will be well worth it. Of those 80, if even a single company becomes as big as Intel, the investment will be paid over twice. Yes, there is every chance that you might back dubious technologies, entrepreneurs or business plans, but the reward is significantly greater. It is approximated that about 27% of US GDP is generated by venture funding and India can get there with some planning, funding and luck.</p>
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		<title>Pune Area Hi-Tech Investments At $1B</title>
		<link>http://punechips.com/pune-investments/</link>
		<comments>http://punechips.com/pune-investments/#comments</comments>
		<pubDate>Mon, 15 Nov 2010 17:06:45 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Networking]]></category>
		<category><![CDATA[pune]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Storage]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[computing]]></category>
		<category><![CDATA[investments]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=197</guid>
		<description><![CDATA[<p><a title="wafer - 3" href="http://www.flickr.com/photos/17425845@N00/3983025303/" target="_blank"><img src="http://farm3.static.flickr.com/2463/3983025303_ba4f02e717_m.jpg" border="0" alt="wafer - 3" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983025303/" target="_blank">oskay</a></small></p>
<p>On November 11, 2010, <a title="Pune Mirror" href="http://punemirror.in" target="_blank">Pune Mirror</a> did a story on investments related to Storage, Networking and Computing chips in Pune. The story is not available online unfortunately, but can be read in the e-Paper version, under &#8216;City&#8217; section, Page 07. For those who are interested in reading this article, we are uploading a scanned copy of this story. Read it here: <a title="Pune Mirror Story on Pune Area Investments" href="http://punechips.com/wp-content/uploads/2010/11/PuneMirrorArticle.pdf" target="_blank">Pune Area Hi-Tech Investments Total [...]<br />
<p>Continue reading <a href="http://punechips.com/pune-investments/">Pune Area Hi-Tech Investments At $1B</a></p>]]></description>
			<content:encoded><![CDATA[<p><a title="wafer - 3" href="http://www.flickr.com/photos/17425845@N00/3983025303/" target="_blank"><img src="http://farm3.static.flickr.com/2463/3983025303_ba4f02e717_m.jpg" border="0" alt="wafer - 3" /></a><br />
<small><a title="Attribution License" href="http://creativecommons.org/licenses/by/2.0/" target="_blank"><img src="http://punechips.com/wp-content/plugins/photo-dropper/images/cc.png" border="0" alt="Creative Commons License" width="16" height="16" align="absmiddle" /></a> <a href="http://www.photodropper.com/photos/" target="_blank">photo</a> credit: <a title="oskay" href="http://www.flickr.com/photos/17425845@N00/3983025303/" target="_blank">oskay</a></small></p>
<p>On November 11, 2010, <a title="Pune Mirror" href="http://punemirror.in" target="_blank">Pune Mirror</a> did a story on investments related to Storage, Networking and Computing chips in Pune. The story is not available online unfortunately, but can be read in the e-Paper version, under &#8216;City&#8217; section, Page 07. For those who are interested in reading this article, we are uploading a scanned copy of this story. Read it here: <a title="Pune Mirror Story on Pune Area Investments" href="http://punechips.com/wp-content/uploads/2010/11/PuneMirrorArticle.pdf" target="_blank">Pune Area Hi-Tech Investments Total $1B</a></p>
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		<title>Event: Storage and Networking Protocols for the Next Generation</title>
		<link>http://punechips.com/storage-and-networking-protocol/</link>
		<comments>http://punechips.com/storage-and-networking-protocol/#comments</comments>
		<pubDate>Tue, 05 Oct 2010 17:06:35 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[event]]></category>
		<category><![CDATA[Networking]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Storage]]></category>
		<category><![CDATA[technology]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=183</guid>
		<description><![CDATA[<div id="attachment_184" class="wp-caption alignnone" style="width: 743px"><a href="http://punechips.com/wp-content/uploads/2010/10/image001.jpg"><img class="size-large wp-image-184 " title="Flier: Howard Goldstein's lecture for PuneChips" src="http://punechips.com/wp-content/uploads/2010/10/image001-733x1024.jpg" alt="Flier: Howard Goldstein's lecture for PuneChips" width="733" height="1024" /></a><p class="wp-caption-text">PuneChips Event: Storage and Networking Protocols for the next generation</p></div>
<p>This is a PuneChips event</p>
<p>What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein<br />
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune<br />
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)</p>
<p><a href="http://punechips.com/storage-and-networking-protocol/" [...]<br />
<p>Continue reading <a href="http://punechips.com/storage-and-networking-protocol/">Event: Storage and Networking Protocols for the Next Generation</a></p>]]></description>
			<content:encoded><![CDATA[<div id="attachment_184" class="wp-caption alignnone" style="width: 743px"><a href="http://punechips.com/wp-content/uploads/2010/10/image001.jpg"><img class="size-large wp-image-184 " title="Flier: Howard Goldstein's lecture for PuneChips" src="http://punechips.com/wp-content/uploads/2010/10/image001-733x1024.jpg" alt="Flier: Howard Goldstein's lecture for PuneChips" width="733" height="1024" /></a><p class="wp-caption-text">PuneChips Event: Storage and Networking Protocols for the next generation</p></div>
<p>This is a PuneChips event</p>
<p>What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein<br />
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune<br />
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)</p>
<p>Registration and Fees: This is a <strong>FREE</strong> event. Seating is limited. To attend, please RSVP: <a href="mailto:sulekha.thakkar@qlogic.com" target="_blank">sulekha.thakkar@qlogic.com</a>.</p>
<div id="_mcePaste">For more details on Howard&#8217;s talk, please see the attached flier.</div>
<div id="_mcePaste">This event is sponsored by <a title="QLogic" href="http://www.qlogic.com" target="_blank">QLogic</a>, a global leader and technology innovator in high performance networking, and supported by <a title="ISA" href="http://www.isaonline.org" target="_blank">ISA </a>(Indian Semiconductor Association), the premier trade body Indian Electronic System Design and Manufacturing Industry.</div>
<div></div>
<div id="_mcePaste"><a title="PuneChips" href="http://www.punechips.com" target="_blank">PuneChips </a>is the forum for semiconductor, EDA and applications designers in and around Pune. It was formed to foster an environment for the growth of semiconductor, EDA and applications companies in and around Pune. For more details, visit our website at www.punechips.com. If you wish to contribute to the community, please join the PuneChips group on groups.google.com. You can also join the PuneChips group on LinkedIn.</div>
<div></div>
<div id="_mcePaste">Please forward this e-mail to anyone in Pune interested in semiconductors, chip design and verification, VLSI design, and embedded design.</div>
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		<title>Electronics Packaging Presentation now available</title>
		<link>http://punechips.com/electronics-packaging-presentation-now-available/</link>
		<comments>http://punechips.com/electronics-packaging-presentation-now-available/#comments</comments>
		<pubDate>Mon, 02 Aug 2010 10:05:08 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[event report]]></category>
		<category><![CDATA[pune]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[packaging]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=179</guid>
		<description><![CDATA[<p>Sandeep Sane has shared his presentation with PuneChips. Please download here: <a href="http://punechips.com/wp-content/uploads/2010/08/Electronics-Packaging.pdf">Electronics [...]<br />
<p>Continue reading <a href="http://punechips.com/electronics-packaging-presentation-now-available/">Electronics Packaging Presentation now available</a></p>]]></description>
			<content:encoded><![CDATA[<p>Sandeep Sane has shared his presentation with PuneChips. Please download here: <a href="http://punechips.com/wp-content/uploads/2010/08/Electronics-Packaging.pdf">Electronics Packaging</a></p>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
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