Semiconductor Manufacturing Plant

I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how Korea became the De-facto memory hub. The story of Korea in the 1960s and where India is now is uncannily similar. Hopefully, the Indian Government takes lessons from this and formulates a policy that works here. Let’s look at the points Deepak makes and see what could be applicable in the Indian context:

Agrarian Economy

Like Korea in the 1960s, India today is primarily an agrarian economy, in the sense that a majority (70%+) of its populations lives in villages performing farming or related occupations. As the government is tries to move the teeming masses to higher paying occupations, a focused policy to dominate in particular semiconductor manufacturing segments might just be the ticket. Like Korea did it with memories, India could focus on 3D chips or microprocessors or DSPs.

Chaebols and Access to Capital

Chaebols are classical Korean conglomerates often owned by a single family. All old school major Indian businesses have a similar structure – Tata, Birla, Reliance, Mahindra, Videocon to name a few. These business groups for the longest time have been using funds from successful groups companies to start new ventures. It is not inconceivable that they could be goaded or cajoled to start semiconductor manufacturing in a huge way. In fact, Reliance was to enter the Semiconductor manufacturing space, but the plans were shelved after the crash of 2008. If the Indian government as a matter of policy actually gives easy access to capital for forming semiconductor businesses, these Indian Chaebols could step up to the plate and take on the challenge. They certainly have done similar things in the past and this would be no different.

New Technologies

Starting a manufacturing business from scratch requires that you look at brand new cutting edge technologies without any of the baggage of the past. You don’t have to worry whether a legacy technology could be migrated to the new line. Newer technologies with a clean start can allow Indian semiconductor manufacturers to leapfrog external competition that must worry about process node transition and migration. If executed properly, India can take a huge lead in a particular semiconductor space.

Low Cost Manufacturing Location

India is still far cheaper compared to the US, the EU, Japan and even China. Additionally, it has a deep pool of resources who actually know how semiconductors are built. This is an inherent advantage that Korea did not have in the 1960s when they only had lower cost.

In fact, all the ingredients for a perfect storm, low costs, talent, land, capital availability and successful business houses are present. All it needs is policy implementation. Of course, this blog and many others can talk ad nauseam about the Indian semiconductor policy. The question is whether the governments, state of central, act and help bring visions into reality.

photo credit: oskay

What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu
When: April 28, 2011 from 9:00 am to 6:00 pm
Where: Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008

This event is not free. The fee is Rs. 1000 per person, which is hardly anything in our opinion. You can get a 25% discount if you bring your own laptop and a further 25% discount with a valid student ID. I want to encourage everyone interested to attend this seminar even though it is not free. Please call +91 20 2590 2984 to register. You can view the workshop details here.

About the Speaker
Mr Basu is a Design Engineer with experience in both Digital and Analog Design using a multitude of EDA and simulation tools. He has strong interests in Embedded systems design and multicore code design. He is a Hobby Robotics fan and entrepreneur in a related field. He has a B.Tech (H) ’03  and  M.Tech ’04  from Indian Institute Of Technology , Kharagpur.

He was the Component Design Engineer for Intel India’s first Multicore project where he also co-authored the Enhanced
Structural Tester Based Functional Test methodology for Intel Multicore processors. He was also the Mixed-Signal Design
Consultant for National Semiconductor’s Sponsored Project at IIT Kharagpur.

He is an accomplished researcher and speaker. A few of his research projects include:

• Behavioral Modelling for Mixed Signal Sytems using Verilog-AMS speeding up simulation times by 1000x
• Analysis of spice simualtion engine for simulation speedup
• Multi-core programming using Message Passing Interface and CUDA

Previously, he has done similar seminars on Behavioral Modelling at IIT Kharagpur

SystemVerilog Guru Cliff Cummings is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit this link to register and view the agenda.

 This event is co-sponsored by Qlogic and Cadence who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.

photo credit: yellowcloud

It has been well over twenty five years since Texas Instruments first set up shop in Bangalore. Other global semiconductor vendors have since made Bangalore, and more recently NOIDA, Hyderabad, Pune and Chennai into huge R&D hubs that develop products for global consumption. Indian engineers are now designing latest chips and systems using cutting edge technologies.  However, not a single Indian chip company has emerged onto the global scene given all this teeming talent. This in itself is surprising, as the low cost Indian environment should make hi-tech businesses thrive. It is said that a semiconductor startup in the Silicon Valley has to raise funds in the range of of US $50m – $60m to be successful. With India’s lower costs of engineering resources, this number could be cut by half or a third, and make life much more simple for the VC as well as the entrepreneur. However, we don’t really see this happening. Why? Probably because India lacks the advanced angel investor culture that focusses on funding and advising hi-technology startups.

In this day and age, it is practically impossible to bootstrap a semiconductor startup unless you are Bill Gates. Most startups require funding once they exhaust funds raised from friends, family and founders and it is very early at this stage for venture capitalists who typically do not invest less than $1m. Angel investors typically fill the gap between the friends and family funds and VC funds. It is estimated that in the US, between 300K to 600K angels invest $40B in over 5000 companies per year. However, the risk associated with an angel round is very high and they lose the money outright in many cases. In order to normalize this, they look for investing in companies that have the potential to offer 10x return on investment. Sadly, India does not have a culture of angel investments yet, maybe because the hi-tech industry is immature and there have not been too many successful hi-tech entrepreneurs. It takes one to know one. A few networks exist, but their exposure to hi-tech is very limited. Most invest in businesses they understand.

How do we change this? There is no easy answer, but Indian government resources would be better served towards the creation of an angel fund that exclusively invests in hi-tech rather than dishing out subsidies to build semiconductor fabrication houses (‘fabs’). Fabs are good and they bring jobs, but they are not the best option to build wealth in a coutry like India, where the principle reason for getting fabs seems to be because China has got’em. Creating semiconductor startups that build products using the fabless model, where they actually outsource all manufacturing to an external fab, will build more wealth and have a much greater impact on the Indian GDP. There was a time when every semiconductor company in the world had to have a fab. But not anymore; there are about 200 integrated device manufacturers, 1500 fabless companies and 125 fabs in the world today. This page has some excellent data.

Let’s look at this in a bit more detail. Of those 125 fabs, only the top twelve or so really earn significant revenues. Even among those, the top 4 – TSMC, UMC, SMIC and Global Foundries make 90% of revenue. In all likelihood, they service 90% of all fabless semiconductor companies. Looking at market caps for these 4 fabs, TSMC has a market cap of $62B, UMC $8B, and SMIC $2B. Global foundries is private so the market cap is unknown, but not likely to be more than UMC’s. Compared to this, of the 1500 or so fabless companies, the top 100 companies have revenues much greater than all the fabs in the world, the valuation is far greater than all the fabs in the world. In addition, a fabless semiconductor company can be started and possibly made successful with $50m investment even in the Valley and much lesser in India. By contrast, a 65nm fab requires at least $3B investment and additional subsidies and consumes far more natural resources. It absolutely does not make sense to encourage building fabs at the expense of promoting and nurturing semiconductor startups.

If the $40B or so supposedly lost in the telecom scam were turned into an angel fund, 8000 companies can each get $500K as their angel round. Using a 1% success rate, even if 80 companies make a successful exit, the exercise will be well worth it. Of those 80, if even a single company becomes as big as Intel, the investment will be paid over twice. Yes, there is every chance that you might back dubious technologies, entrepreneurs or business plans, but the reward is significantly greater. It is approximated that about 27% of US GDP is generated by venture funding and India can get there with some planning, funding and luck.

photo credit: oskay

On November 11, 2010, Pune Mirror did a story on investments related to Storage, Networking and Computing chips in Pune. The story is not available online unfortunately, but can be read in the e-Paper version, under ‘City’ section, Page 07. For those who are interested in reading this article, we are uploading a scanned copy of this story. Read it here: Pune Area Hi-Tech Investments Total $1B

Image Sourve: allSAN.com

Howard Goldstein spoke to the PuneChips community on Storage and Networking Protocols earlier this month. His presentation is now available here as a PDF file. Please download as required.

Goldstein Storage Networking – The Path to Performance

PuneChips Event: Storage and Networking Protocols for the next generation

This is a PuneChips event

What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)

Registration and Fees: This is a FREE event. Seating is limited. To attend, please RSVP: sulekha.thakkar@qlogic.com.

Photo courtesy of Exponent, Inc.

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Dr. Sandeep Sane on Electronic Packaging – Materials and Mechanics Challenges
When: Saturday, 10th July 2010, 10:30 am to 12:30 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Electronic Packaging – Materials and Mechanics Challenges
Electronic packaging has typically been defined as providing an enabling function and a space transformer between the IC feature sizes and the board & system level interconnects and over years it has grown to become a ubiquitous part of the overall electronic assembly. In certain market segments, such as flash memories, the package has evolved to become a key product differentiator and performance enabler. The scope of electronic packaging is very broad across multiple application areas such as CPU’s and Chipsets for the desktop, mobile and server segments, hand-held and wireless devices, telecom components & network processors, and memory devices; with each segment potentially having its unique set of demands and constraints such as the form factor, function, cost, reliability requirements, thermal and electrical performance.

To ensure that right technical and cost-effective solutions are defined, developed and deployed across the different market segments, electronic packaging provides significant research and development challenges and opportunities across multiple disciplines including materials, mechanics, reliability, thermals, high speed interconnects, power delivery and manufacturing.

This presentation will first provide an overview of current and future package technologies and associated demands in the different market segments, followed by focusing on some of the recent progress made in addressing some of the mechanics and materials challenges and highlight opportunities in future packaging technology development.

About the speaker – Dr. Sandeep
Sandeep Sane received his Ph.D. from California Institute of Technology, Pasadena in Aerospace Engineering with major in Solid Mechanics. He holds M.S. in Aeronautics, California Institute of Technology and B.Tech in Mechanical Engineering from Indian Institute of Technology, Bombay (Mumbai).

Sandeep is currently a Technology Development manager in the Assembly and Test Technology Development (ATTD) organization, Intel Corp., Chandler. He manages a technical team of 30 engineers including an experimental mechanics laboratory; equipped with start of art analysis and validation metrologies. His team is chartered to deliver fundamental understanding of various mechanical issues in electronic packaging, establish roadmaps for ATTD and work directly with Intel’s customers (OEM/ODMs) and suppliers to resolve mechanical issues. He is also responsible for delivering novel mechanical analysis, material characterization and validation techniques to help optimize design, material and process changes to deliver reliable and cost effective solutions for Intel’s packaging technologies. Sandeep has led and participated in numerous taskforces and management review boards to resolve critical issues in a timely manner impacting Intel’s bottom-line. Prior to joining Intel, he was a Development Staff Engineer with IBM, Endicott, NY, working in Mechanical & Thermal Analysis group.

Sandeep has filed for more than 15 patents and have published several technical articles in various conferences and journal proceedings. He is also a recipient of numerous awards across Intel for his technical contributions. He is a member of ASME, IEEE and an active member of organizing committees for ASME and IEEE conferences. He also serves on Industrial Advisory Board for Mechanical Engineering at University of Colorado, Boulder and NSF review committee.

About Venture Center
Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips
PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips.  Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.