Karnataka government says : “ESDM is an emerging sector aligned to the professional skills, knowledge base and managerial talent available in the state of Karnataka in the field of VLSI, Semiconductor chip design and embedded software. As of 2012, Karnataka has 85 chip design houses, 336 R&D facilities, delivers outsourced information technology solutions to over 400 of the global Fortune 500 companies and has over 6 lakh technology professionals employed in Bangalore alone” 

Below is the document policy :

STEPS :

1) SPECIFICATION :

Lot of activity from gathering market requirement to deciding the technical aspect is done first. This is the crucial step as it will affect the future of the product. Here, vendors may want to get feedback from potential customers on what they are looking for. Once this is done  final specification sheet with all possible technical details is made and handed over to the next team.

2) ARCHITECTURE :

This is where the main work starts. With the help of the specification sheet the target IC’s architecture is decided and a layout for same is created by design engineers using EDA tools. In the next step this architecture is implemented and tested with the help of programming language and tools.

Flowchart For VLSI Design Flow

3) RTL CODING :

RTL is an acronym for register transfer level. This implies that the VHDL code written based on the architecture describes how data is transformed as it is passed from register to register. This is how a 2-input MUX looks like :

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity MUX2 is
  port (SEL, A, B: in STD_LOGIC;
  F : out STD_LOGIC);
end;

architecture BEHAVIOUR of MUX2 is

begin
  -- descibed using a single process
end;

4) RTL VERIFICATION :

Register Transfer Level (RTL) simulation and verification is one of the important step. This ensures that the design is logically correct and without major timing errors. It is advantageous to perform this step, especially in the early stages of the design. Synopsys simulation tools may be used to perform RTL verification. A test bench file may be used here for verification.

5) SYNTHESIS :

This is where the design now start to get physical. Logic synthesis is a process by which the  desired circuit behavior i.e. Register Transistor Level is turned into a design in terms of logic gates which drives the circuit or architecture.  This is done with the help of  FPGA/CPLD/ASIC hardware tools. These target boards may be accessed using the IDE’s provided by specific vendor.

6) BACK – END :

Here the final tested design after synthesis is given to the IC manufacturer.

7) TAPE – OUT :

Tape out is the process under back end only where the final result of FRONT – END (first 5 steps) is provided to the manufacturer in form of photomask. Then the manufacturer performs wafer processing, packaging, testing, delivery of samples to test the physical IC.

8) TO FOUNDRY :

Once the sample are tested and all the requirement are furnished the design is sent for mass production.

NOTE : 

While learning and writing about this blog topic, I found that not a single standardized document is available for same. If readers of this blog post know about any, then do share by commenting below.

Below one may see how Cloud Computing & EDA tools are evolving :

HOW IT WORKS :

1. A user with Cloud Based License logs into an interface which gives access to EDA tools.
2. Then user installs EDA tool on desired platform.
3. User may add other contributors/users to same interface.
4. Once tools are configured, user may use EDA tool to create projects.
5. Now user has the option to log out and stop the instance which was created so that he gets billed only for the time he used the service.

PROS :

1. No need to worry about having a desktop with licensed EDA tool.
2. Work on the move.
3. Pay as you go model.
4. Multiple user option : Good for industry.
5. Academic institutes may benefit a lot.
6. Apart from EDA tool, get access to lot of analytics.
7. Labs may become inexpensive and truly virtual.

CONS :

1. Not suitable for people with slow internet connectivity. Good bandwidth required.
2. It’s important to stop the service when not is use, other wise it reflects on the bill.
3. One may have to pay for the service which allows interaction with EDA tools, apart from regular usage.

Overall it’s a win win situation for users and it will truly change the way EDA tools are accessed and more focus on task in hand rather than worrying about configuring and maintaining systems as it’s done now.

]]> http://punechips.com/cloud-computing-eda/feed/ 0 http://punechips.com/eda-licensing-models/?utm_source=rss&utm_medium=rss&utm_campaign=eda-licensing-models http://punechips.com/eda-licensing-models/#comments Fri, 29 Mar 2013 16:32:43 +0000 Chetan Patil http://punechips.com/?p=455 Electronic Design Automation (EDA) products by various vendors are sold on the basis of licensing models. In the chart shown below one can see the various EDA licensing models which are available and a buyer/user can pick the licensing model as per the requirement.

Read more on EDA LICENSING MODELS…

(Image taken from DEIT website)

Key highlights of NPE are :

Full policy draft may be found here.

As per Dept. of Electronics & Information Technology following is the projection for Electronics Demand & Production :

(Image taken from DEIT website)

To address the issue of infrastructure, GOI has come up with a scheme for Electronics Manufacturing Cluster which provides 50% of the cost of upgrading infrastructure and logistics as grant in aid from Government. Also as per the Union budget 2013 boost will be given to those products which will be Made in India. It’s time for Indian Electronics Industry to make the most of NPE as the absence of this government initiative, can cater to a demand of USD 100 billion by 2020 as against demand of USD 400 billion.

(Image provided by Hardware Freedom Day community)

If you want to celebrate the HFD in your city/community then here is the guide to do so. Even one can promote the Hardware Freedom Day using various mode, like blogging the way PuneChips is doing. Do check if any community is organizing same event nearby. Let’s support Open Hardware!

]]> http://punechips.com/hardware-freedom-day/feed/ 0 http://punechips.com/virtual-prototyping/?utm_source=rss&utm_medium=rss&utm_campaign=virtual-prototyping http://punechips.com/virtual-prototyping/#comments Tue, 19 Mar 2013 10:15:18 +0000 Chetan Patil http://punechips.com/?p=325 When it comes to development of a hardware platform it is a very costly and time consuming affair. It’s very important to be sure about the platform which is being created will live up to the expectation and standards. For this there should be a way by which software development can begin well before a physical prototype is available. Such process will also  help in generating the feedback mechanism for hardware manufacturer. In order to do so, electronic design automation industry has come up with the concept of Virtual Prototyping, where in using computer aided tools validation is done before making the physical prototype.

Below is the comparison of Physical and Virtual prototyping as per the white paper by Mentor Graphics :

Apart from other important benefits, the main advantages which Virtual prototyping provides are :

Read more on VIRTUAL PROTOTYPING…

When it comes to development of a hardware platform it is a very costly and time consuming affair. It’s very important to be sure about the platform which is being created will live up to the expectation and standards. For this there should be a way by which software development can begin well before a physical prototype is available. Such process will also  help in generating the feedback mechanism for hardware manufacturer. In order to do so, electronic design automation industry has come up with the concept of Virtual Prototyping, where in using computer aided tools validation is done before making the physical prototype.

As of now the main processor architectures which have been targeted using this prototyping are x86, ARM, Power PC and MIPS. EDA tools for same are available from the vendors like Mentor Graphics which has Vista Virtual Prototyping, Synopsis has Virtualizer etc. There is also an open source alternative in form of QEMU.

Below is the comparison of Physical and Virtual prototyping as per the white paper by Mentor Graphics :

(Image taken from White Paper by Mentor Graphics)

Apart from other important benefits, the main advantages which Virtual prototyping provides are :

• Early validation of software against hardware.
• Detailed hardware architecture and RTL design.
• Reduction in the efforts of both hardware and software verification.

To speed the virtual prototyping there are kits which are available called virtual development kits. If you wan to learn more about virtual prototyping then check the above white paper and there is another White Paper on Virtual Prototyping by Synopsis. It would be interesting to see in near future how the EDA industry speeds up the development in form of tools and kits for virtual prototyping and how virtual prototyping will evolve as compared to emulation and simulation.

]]>

1. Electronic Design Systems
2. Embedded Software Systems.

The deadline for abstract submission is September 15th, 2012.

Shortlisted entries will be given opportunity to make poster presentation or demo in the exhibit area at a special session of VLSI 2013 conference to be held in January 2013 in Pune, India. Participation certificates will be given to all the short listed entries. Award-winning entries will be recognized during the conference banquet …

The conference will also award limited number of fellowships, based on need and merit, to partially cover expenses of attendees from India. Students with short-listed design contest entries will be given preference. Fellowship application details will be posted at the website.

Abstracts may only be submitted on-line.

VLSI Design Conference 2013: Design Contest Poster

What: Talk by Robert W. JKembel on Unified Data Center Network
When: Wednesday, 21st March, 2012, 5 pm to 8 pm.
Where: Yashada, Rajbhavan Complex, Baner Road, Pune

Registration and fees: This event is *FREE* for all to attend. Please RSVP to amarjeet.sharma@qlogic.com.

I was given a personal tour by Sandeep Sathe, a Sr. Development manager at Nvidia and also met with Jaya Panvalkar, Sr. Director and head of Pune facilities. There was enough to see and do at this event and unfortunately I was a bit short on time. It would have taken a good two hours for a complete walk-through, so I decided to spend more time on the GPU/HPC section though the Tegra based mobile device section was also quite impressive. It’s been a while since I actually installed a new graphics card in a desktop (actually, it’s been a while since I used a desktop), but graphics cards have come a long way! Nvidia is using standard PCI Express form factor cards for the GPU modules with on-board fans and DVI connectors.

The following are key takeaways from the demo stations I visited

GeForce Surround 2-D
Here, Nvidia basically stretches the game graphics from a single monitor to three monitors. Great for gamers as it gives a fantastic feel for peripheral vision. The game actually doesn’t have to support this. The graphics card takes care of it. The setup here is that while the gamer sits in front of the main monitor, he also sees parts of the game in his peripheral vision in two other monitors that are placed at an angle to the main monitor. I played a car rally game and the way roadside trees, objects moved from the main monitor to the peripheral vision monitors was quite fascinating.

GeForce 3-D Vision Surround
This is similar to the above, but with 3D. You can completely immerse yourself in the game. This sort of gaming setup is now forcing monitor manufacturers to develop monitors with ultra small bezel widths. I suppose at some point in the next few years, we will be able to seamlessly merge graphics from different monitors into one continuous collage without gaps.

Powerwall Premium Mosaic
Powerwall is a eight monitor setup driven by the Quadro professional graphics engine. Two Quadro modules fit into one Quadroplex industrial PC to drive four monitors. Projectors can also be used in place of monitors to create a seamless view. The display was absolutely clear and highly detailed. The Powerwall is application transparent. Additional coolness factor – persistence data is saved so you don’t lose the image during video refresh and buffer swaps. This is most certainly a tool intended for professionals who need high quality visuals and computing in their regular work. Examples are automotive, oil and gas, stock trading.

PhysX Engine
PhysX is a graphics engine that infuses real time physics into games or applications. It is intended to make objects in games or simulations move as they would in real life. To me this was very disruptive, and highlight of the show. You can read more about PhysX here. It is very clear how PhysX would change gaming. The game demo I watched had several outstanding effects: dried leaves moving away from the character as he walks through a corridor, glass breaking into millions of shards as it would in real life. Also running was a PhysX simulation demo that would allow researchers to actually calculate how objects would move in case of a flood. What was stunning was that the objects moved differently every time as they would in real life. PhysX runs on Quadro and Tesla GPUs. It is interesting to note that Ra.One special effects were done using PhysX.

3D photos and movies
Next couple of demos demonstrated 3D TV and photo technology using Sony TVs and a set of desktops/laptops. Notably, the Sony 3D glasses were much more comfortable compared to others. Nvidia is working with manufacturers to create more comfortable glasses. There was also a Toshiba laptop that uses a tracking eye camera to display a 3D image to the viewer regardless of seating position without glasses. It was interesting. However, the whole 3D landscape need a lot of work from the industry before it can become mainstream.

Optimus
What was explained to me was that Optimus allows laptops to shut off GPUs when they are not needed. They can be woken up when high performance work is required. This would be automatic and seamless, similar to how power delivery is in on a Toyota Prius. This sort of a technology is not new to computing – a laptop typically puts a lot of components to sleep/hibernate when not being used, but the GPU is not included.

Quadro Visualizations
This allows 2D/3D visualizations for automotive, architectural and similarly complex systems for up to one thousand users at a time. You can easily change colors, textures, views so everyone can comment and give constructive feedback. I was not sure if the design can be changed on the fly as well. Nvidia is working with ISVs like Maya and Autodesk on this.

Tesla
Tesla GPUs use chips that are used for high performance computing and not rendering, which is different from what Nvidia typically does. The Tesla modules do not have any video ports! It has a heterogeneous GPU/CPU architecture that saves power. In fact, the SAGA-220 supercomputer, dubbed India’s fastest, at ISRO’s Vikram Sarabhai Space Center facility uses 2070 Tesla GPUs along with 400 Intel Xeon processors. In addition to supercomputing, Tesla is very useful in 3D robotic surgery, 3D ultrasound, molecular dynamics, oil and gas, weather forecasting and many more applications.

Tegra Mobile Processor
Next few demos showcased the Tegra mobile applications processor based on ARM Cortex A9 cores. The HD quality graphics and imaging were impressive. It is clear that smartphones and tablets of the day are clearly far more powerful compared to desktops of yesteryear and can support highly impressive video and audio in a very handy form factor.

In all, I had a great time. As I mentioned earlier, Nvidia along with other tech companies in Pune should hold more of these kinds of events to give technology exposure to the larger population in general. I think it is important for people to know that the stuff that makes Facebook run is the real key and that is where the coolness is.

Bangalore based startup, Saankhya Labs’ Universal TV demodulator chip has been nominated as one of the finalists for the prestigious ACE awards instituted by UBM (publisher of EETimes and EDN) in the SoC category.

Viewed in its rightful context, this is a major achievement. They are competing with Cadence, Calxeda, ST Micro and Xilinx. Please vote for them and create history.

Visit http://www.edn.com/info/2399-2012_ACE_Awards_Ultimate_Products.php to vote.

The $45 Akash

The irrepressible Mr. Sibal has done it again. He thinks that a high powered govt. committee can supervise the manufacture of a mil-spec Akash (Siblet – I have borrowed this name from @comicproject on Twitter) through BEL and ECIL for $45. Let me get this straight – a few current and retired bureaucrats who probably majored in English or Hindi Lit will now tell some folks  at a sarkari company how to design a tablet and get it done. Secondly, he wants the tab to be Indegenized.  This is getting beyond ridiculous to say the least.

Let’s count the reasons:

#1: While DataWind may not be the best manufacturer, why not eject them for someone better?
#2: Do we really thing that BEL and ECIL have the wherewithal to actually build a device that customers will like. Name the last consumer electronics box either of these companies built? The answer is none! Even Videocon would be better suited than either of these. I have closely observed the inner workings of BEL in an earlier life – not pretty! They might turn around and give the contract back to DataWind.
#3: Why MIL-SPEC? What the heck is IIT Jodhpur thinking?
#4: What’s with the $45 price – you can’t even buy a decent phone with it, let alone a tablet.
#5: Why the insistence on Indigenization? The current Akash imports about 70% of components and it is impossible to indigenize it any further unless India starts manufacturing chips, LCD screens and other related electronics overnight.

Bold vision is bold only if supported by a path to getting there. Otherwise, it just looks stupid and megalomaniacal.

This is exactly the reason why India needs its own Sony and disband the departments of science and technology and telecommunications, and others but that is another story!

Semiconductor Manufacturing Plant

I came across a blog written by Deepak Sekar, the Chief Scientist at Monolithic 3D and he makes several interesting points as to how Korea became the De-facto memory hub. The story of Korea in the 1960s and where India is now is uncannily similar. Hopefully, the Indian Government takes lessons from this and formulates a policy that works here. Let’s look at the points Deepak makes and see what could be applicable in the Indian context:

Agrarian Economy

Like Korea in the 1960s, India today is primarily an agrarian economy, in the sense that a majority (70%+) of its populations lives in villages performing farming or related occupations. As the government is tries to move the teeming masses to higher paying occupations, a focused policy to dominate in particular semiconductor manufacturing segments might just be the ticket. Like Korea did it with memories, India could focus on 3D chips or microprocessors or DSPs.

Chaebols and Access to Capital

Chaebols are classical Korean conglomerates often owned by a single family. All old school major Indian businesses have a similar structure – Tata, Birla, Reliance, Mahindra, Videocon to name a few. These business groups for the longest time have been using funds from successful groups companies to start new ventures. It is not inconceivable that they could be goaded or cajoled to start semiconductor manufacturing in a huge way. In fact, Reliance was to enter the Semiconductor manufacturing space, but the plans were shelved after the crash of 2008. If the Indian government as a matter of policy actually gives easy access to capital for forming semiconductor businesses, these Indian Chaebols could step up to the plate and take on the challenge. They certainly have done similar things in the past and this would be no different.

New Technologies

Starting a manufacturing business from scratch requires that you look at brand new cutting edge technologies without any of the baggage of the past. You don’t have to worry whether a legacy technology could be migrated to the new line. Newer technologies with a clean start can allow Indian semiconductor manufacturers to leapfrog external competition that must worry about process node transition and migration. If executed properly, India can take a huge lead in a particular semiconductor space.

Low Cost Manufacturing Location

India is still far cheaper compared to the US, the EU, Japan and even China. Additionally, it has a deep pool of resources who actually know how semiconductors are built. This is an inherent advantage that Korea did not have in the 1960s when they only had lower cost.

In fact, all the ingredients for a perfect storm, low costs, talent, land, capital availability and successful business houses are present. All it needs is policy implementation. Of course, this blog and many others can talk ad nauseam about the Indian semiconductor policy. The question is whether the governments, state of central, act and help bring visions into reality.

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik
When: July 30, 2011 from 10:30 am to 12:00 noon
Where: Venture Center, NCL Innovation Park, Pashan Road

PCI Express Architecture and Applications for FPGAs

Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards  to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI Express^TM. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running Windows^TM, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.

About the speaker: Kiran Puranik

Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.

photo credit: Patrick Hoesly

Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online.

Click here to download the PDF.

This event is jointly brought to you by PuneChips and LSI Corporation.

What: Technical Talk by Dr. T.R. Ramachandran on Building and Autonomoous and Scalable Semiconductor VLSI Business
Where: Sargam Auditorium, 4th floor, LSI India Research & Development Private Limited,  T +91 20 4010 4700
When: Wednesday, July 13th 2011, 9:30am-11am. Please arrive by 9:00am for security registration and snack

RSVP: Reshma Arthani:  Reshma.Artani@lsi.com, Mobile: +91.992.320.3557

Abstract:

The presentation focuses on effective ways to build autonomous and scalable semiconductor VLSI businesses. The trends in the VLSI industry and inherent challenges of growth make autonomy & scale-building essential elements of long-term success. This is particularly relevant to emerging geographies like India where there is increased focus on enhancing end-to-end capabilities and overall management.

About the speaker:

T. R. Ramachandran is Senior Director for Product Operations in the Storage Peripherals Division at LSI. In this role, he reports to the Senior Vice President and General Manager of the division and is responsible for the operations infrastructure, business processes, IP and customer program management across the entire product lifecycle from planning through manufacturing ramp for LSI’s highest volume semiconductor business. Before assuming this role, TR held a number of positions in LSI where he brought to bear a unique blend of expertise in a range of areas from business, operations & program management, strategic/competitive analysis, large-scale M&A and business transformations, global product development and deployment, and supplier & manufacturing management. He lives in the United States in Northern California, and is keenly interested in various aspects of technology & broader public policy as well as problems of scale tied to private, public and/or non-governmental sectors.

TR received a Bachelor’s degree in Metallurgical Engineering from IIT-M (Indian Institute of Technology in Madras/Chennai) and is a recipient of the Dr. Dhandapani Prize from IIT-M and the Vidya Bharati Prize conferred by the Indian Institute of Metals. He received his Masters and Ph.D. degrees in Materials Science from the University of Southern California, Los Angeles. His Ph.D. was focused on structural and optical studies of semiconductor thin films & quantum dot nanostructures and innovative forays into nanotechnology using scanning probe microscopes.

photo credit: oskay

What: A seminar on Digital Design and Prototyping with Verilog by Mr. Basu
When: April 28, 2011 from 9:00 am to 6:00 pm
Where: Classroom E, 100 NCL Innovation Park, Dr. Homi Bhabha Road, Pune 411008

This event is not free. The fee is Rs. 1000 per person, which is hardly anything in our opinion. You can get a 25% discount if you bring your own laptop and a further 25% discount with a valid student ID. I want to encourage everyone interested to attend this seminar even though it is not free. Please call +91 20 2590 2984 to register. You can view the workshop details here.

About the Speaker
Mr Basu is a Design Engineer with experience in both Digital and Analog Design using a multitude of EDA and simulation tools. He has strong interests in Embedded systems design and multicore code design. He is a Hobby Robotics fan and entrepreneur in a related field. He has a B.Tech (H) ’03  and  M.Tech ’04  from Indian Institute Of Technology , Kharagpur.

He was the Component Design Engineer for Intel India’s first Multicore project where he also co-authored the Enhanced
Structural Tester Based Functional Test methodology for Intel Multicore processors. He was also the Mixed-Signal Design
Consultant for National Semiconductor’s Sponsored Project at IIT Kharagpur.

He is an accomplished researcher and speaker. A few of his research projects include:

• Behavioral Modelling for Mixed Signal Sytems using Verilog-AMS speeding up simulation times by 1000x
• Analysis of spice simualtion engine for simulation speedup
• Multi-core programming using Message Passing Interface and CUDA

Previously, he has done similar seminars on Behavioral Modelling at IIT Kharagpur

SystemVerilog Guru Cliff Cummings is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to  re-engage with him. This event is completely free, but registration is required. Please visit this link to register and view the agenda.

 This event is co-sponsored by Qlogic and Cadence who I must thank profusely on behalf of the PuneChips community. It is not very often that internationally renowned experts visit our city and hold free seminars, but QLogic and Cadence have made it possible. So, I encourage everyone who has any interest in SystemVerilog to attend and participate.

photo credit: cote

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Ashim Patil on Radio Frequency Identification
When: Saturday, 16th April 2011, 10:30 am to 12:00 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Radio Frequency Identification
Product, people and document identification is now a huge challenge. Radio Frequency Identification (RFID) offers an active ID mechanism that requires no intervention on the part of the user.  This presentation will introduce  the RFID technology, positioning and its variants. The speaker will also introduce Near Field Communication (NFC) and its differences with regular RFID. RFID and NFC applications across several verticals in India will also be discussed.

About the Speaker – Ashim Patil 

Mr. Ashim A Patil is the MD & CEO of Infotek Software & Systems Pvt Ltd., also known as i-TEK. Under his leadership i-TEK is one of the leading RFID (Radio Frequency Identification) system integration companies in India. i-TEK has several live RFID sites across verticals like Manufacturing, Banking, Education and Healthcare. i-TEK has to its credit RFID applications like File & Document Tracking, Asset Management, Stores Management, Automatic Vehicle Identification, HNI Tracking and many more, deployed at leading organisations in India.

Mr. Patil has completed his engineering degree from University of Pune in 1998. Fresh out of college, he began his entrepreneurial journey starting an Aptech franchisee which he sold in 3 yrs. After that, he took over an ailing software company in Pune which later on became today’s successful i-TEK under his able guidance. He shifted the focus to RFID when not many were even aware what the acronym stands for.

photo credit: kalleboo

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Gandhar Gokhale on Moving from 3G to 4G
When: Saturday, 26th March 2011, 10:30 am to 12:00 noon.
Where: Venture Center, Classroom E, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Mobile Networks - Moving from 3G to 4G
This presentation will be an introduction to the mobile network evolution. It’ll run through the evolution of generations of mobile networks to the upcoming 4G.  The radio interface and terrestrial network evolution in each generation will be briefly touched upon. The LTE (Long Term Evolution) as the candidate technology for 4G shall be explored. We’ll conclude by discussing how these generations have impacted or shall impact our lives.

About the Speaker – Gandhar Gokhale
Gandhar Gokhale is a software architech with LSI Corporation. He has more than 12 years of Network Software development and Network Security experience. He completed his  M.E. (Telecom) from IISc Bangalore and B.E. (Electronics) from WCE Sangli.

photo credit: yellowcloud

It has been well over twenty five years since Texas Instruments first set up shop in Bangalore. Other global semiconductor vendors have since made Bangalore, and more recently NOIDA, Hyderabad, Pune and Chennai into huge R&D hubs that develop products for global consumption. Indian engineers are now designing latest chips and systems using cutting edge technologies.  However, not a single Indian chip company has emerged onto the global scene given all this teeming talent. This in itself is surprising, as the low cost Indian environment should make hi-tech businesses thrive. It is said that a semiconductor startup in the Silicon Valley has to raise funds in the range of of US $50m – $60m to be successful. With India’s lower costs of engineering resources, this number could be cut by half or a third, and make life much more simple for the VC as well as the entrepreneur. However, we don’t really see this happening. Why? Probably because India lacks the advanced angel investor culture that focusses on funding and advising hi-technology startups.

In this day and age, it is practically impossible to bootstrap a semiconductor startup unless you are Bill Gates. Most startups require funding once they exhaust funds raised from friends, family and founders and it is very early at this stage for venture capitalists who typically do not invest less than $1m. Angel investors typically fill the gap between the friends and family funds and VC funds. It is estimated that in the US, between 300K to 600K angels invest $40B in over 5000 companies per year. However, the risk associated with an angel round is very high and they lose the money outright in many cases. In order to normalize this, they look for investing in companies that have the potential to offer 10x return on investment. Sadly, India does not have a culture of angel investments yet, maybe because the hi-tech industry is immature and there have not been too many successful hi-tech entrepreneurs. It takes one to know one. A few networks exist, but their exposure to hi-tech is very limited. Most invest in businesses they understand.

How do we change this? There is no easy answer, but Indian government resources would be better served towards the creation of an angel fund that exclusively invests in hi-tech rather than dishing out subsidies to build semiconductor fabrication houses (‘fabs’). Fabs are good and they bring jobs, but they are not the best option to build wealth in a coutry like India, where the principle reason for getting fabs seems to be because China has got’em. Creating semiconductor startups that build products using the fabless model, where they actually outsource all manufacturing to an external fab, will build more wealth and have a much greater impact on the Indian GDP. There was a time when every semiconductor company in the world had to have a fab. But not anymore; there are about 200 integrated device manufacturers, 1500 fabless companies and 125 fabs in the world today. This page has some excellent data.

Let’s look at this in a bit more detail. Of those 125 fabs, only the top twelve or so really earn significant revenues. Even among those, the top 4 – TSMC, UMC, SMIC and Global Foundries make 90% of revenue. In all likelihood, they service 90% of all fabless semiconductor companies. Looking at market caps for these 4 fabs, TSMC has a market cap of $62B, UMC $8B, and SMIC $2B. Global foundries is private so the market cap is unknown, but not likely to be more than UMC’s. Compared to this, of the 1500 or so fabless companies, the top 100 companies have revenues much greater than all the fabs in the world, the valuation is far greater than all the fabs in the world. In addition, a fabless semiconductor company can be started and possibly made successful with $50m investment even in the Valley and much lesser in India. By contrast, a 65nm fab requires at least $3B investment and additional subsidies and consumes far more natural resources. It absolutely does not make sense to encourage building fabs at the expense of promoting and nurturing semiconductor startups.

If the $40B or so supposedly lost in the telecom scam were turned into an angel fund, 8000 companies can each get $500K as their angel round. Using a 1% success rate, even if 80 companies make a successful exit, the exercise will be well worth it. Of those 80, if even a single company becomes as big as Intel, the investment will be paid over twice. Yes, there is every chance that you might back dubious technologies, entrepreneurs or business plans, but the reward is significantly greater. It is approximated that about 27% of US GDP is generated by venture funding and India can get there with some planning, funding and luck.

photo credit: oskay

On November 11, 2010, Pune Mirror did a story on investments related to Storage, Networking and Computing chips in Pune. The story is not available online unfortunately, but can be read in the e-Paper version, under ‘City’ section, Page 07. For those who are interested in reading this article, we are uploading a scanned copy of this story. Read it here: Pune Area Hi-Tech Investments Total $1B

Image Sourve: allSAN.com

Howard Goldstein spoke to the PuneChips community on Storage and Networking Protocols earlier this month. His presentation is now available here as a PDF file. Please download as required.

Goldstein Storage Networking – The Path to Performance

PuneChips Event: Storage and Networking Protocols for the next generation

This is a PuneChips event

What: Storage and Networking Protocols for the next generation, a lecture by Howard Goldstein
Where: MCCIA (Sumant Moolgaonkar) Auditorium, Ground floor, A Wing (same building as Crossword Book Store), ICC Trade Tower, Senapati Bapat Road, Pune
When: Tuesday, October 12, from 6:30pm to 8pm (Request to be seated by 6:15pm)

Registration and Fees: This is a FREE event. Seating is limited. To attend, please RSVP: sulekha.thakkar@qlogic.com.

Photo courtesy of Exponent, Inc.

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA

What: Talk by Dr. Sandeep Sane on Electronic Packaging – Materials and Mechanics Challenges
When: Saturday, 10th July 2010, 10:30 am to 12:30 noon.
Where: Venture Center, NCL Innovation Park, Pashan Road

Registration and fees: This event is *FREE* for all to attend. No registration required.

Electronic Packaging – Materials and Mechanics Challenges
Electronic packaging has typically been defined as providing an enabling function and a space transformer between the IC feature sizes and the board & system level interconnects and over years it has grown to become a ubiquitous part of the overall electronic assembly. In certain market segments, such as flash memories, the package has evolved to become a key product differentiator and performance enabler. The scope of electronic packaging is very broad across multiple application areas such as CPU’s and Chipsets for the desktop, mobile and server segments, hand-held and wireless devices, telecom components & network processors, and memory devices; with each segment potentially having its unique set of demands and constraints such as the form factor, function, cost, reliability requirements, thermal and electrical performance.

To ensure that right technical and cost-effective solutions are defined, developed and deployed across the different market segments, electronic packaging provides significant research and development challenges and opportunities across multiple disciplines including materials, mechanics, reliability, thermals, high speed interconnects, power delivery and manufacturing.

This presentation will first provide an overview of current and future package technologies and associated demands in the different market segments, followed by focusing on some of the recent progress made in addressing some of the mechanics and materials challenges and highlight opportunities in future packaging technology development.

About the speaker – Dr. Sandeep
Sandeep Sane received his Ph.D. from California Institute of Technology, Pasadena in Aerospace Engineering with major in Solid Mechanics. He holds M.S. in Aeronautics, California Institute of Technology and B.Tech in Mechanical Engineering from Indian Institute of Technology, Bombay (Mumbai).

Sandeep is currently a Technology Development manager in the Assembly and Test Technology Development (ATTD) organization, Intel Corp., Chandler. He manages a technical team of 30 engineers including an experimental mechanics laboratory; equipped with start of art analysis and validation metrologies. His team is chartered to deliver fundamental understanding of various mechanical issues in electronic packaging, establish roadmaps for ATTD and work directly with Intel’s customers (OEM/ODMs) and suppliers to resolve mechanical issues. He is also responsible for delivering novel mechanical analysis, material characterization and validation techniques to help optimize design, material and process changes to deliver reliable and cost effective solutions for Intel’s packaging technologies. Sandeep has led and participated in numerous taskforces and management review boards to resolve critical issues in a timely manner impacting Intel’s bottom-line. Prior to joining Intel, he was a Development Staff Engineer with IBM, Endicott, NY, working in Mechanical & Thermal Analysis group.

Sandeep has filed for more than 15 patents and have published several technical articles in various conferences and journal proceedings. He is also a recipient of numerous awards across Intel for his technical contributions. He is a member of ASME, IEEE and an active member of organizing committees for ASME and IEEE conferences. He also serves on Industrial Advisory Board for Mechanical Engineering at University of Colorado, Boulder and NSF review committee.

About Venture Center
Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

About PuneChips
PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips.  Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

photo credit: oskay

This is the second in the blog series titled Field Manual for Verification Planning written for PuneChips by Suhas Belgal . The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.  

Welcome to the second article in the Chip Design Verification blog series. In this article, we will look at the Test-plan development part of the verification program. We are going to explore the method to the madness of developing effective test-plans.  

Some of the questions that come to the mind are: how do we know if the test-plan is complete? How do we map the test-plan to the ‘tests’? How do we ensure coherency between the test-plan and the test data base throughout the project (and beyond)? What’s a good test-plan template? How should the cases be organized? What additional data or information needs to be in the test-plan? Throughout this article, we will address these questions. What one should expect here is not a ready-made solution, but the underlying philosophy, various options available for implementation and key considerations. As mentioned in the introductory article, there is an ‘intellectual part’ which requires the best and the brightest engineering mind and cannot be substituted by any tool or practice. This will be clearly identified wherever applicable.  

Example

Let’s revisit our example. The DUT is a simple SOC with some standard SOC components – a host processor, a co-processor (such as a DSP or some such computational element), internal buses for both control and high speed data transfers, memory sub-system (DDRs, SRAMs), peripheral IO interfaces such as USB, UART, and internal SOC control elements such as IO muxes, clock/power management unit, interrupt management unit.  

The following block diagram illustrates our example. 

Example DUT

What Rather Than how

The first step in any verification program is to review the Design/Architecture Specification documents along with any other relevant supporting documents such as ‘Standards Specifications’. This becomes the basis of what needs to be tested. At this stage, don’t worry about the how this block or chip needs to be tested or any other logistical issues such as schedule, simulation speed, resources etc., as it would cause unnecessary distraction, and might cause you to overlook some of the test-cases. Any cracks at this stage are the most expensive. Achieving a high quality list of ‘what’ needs testing is indeed an intellectual process – this list forms the ‘denominator’ in the coverage ratio – regardless of tool or method used for measuring coverage.  

Given the importance, this step needs undivided attention. Block off time on your calendar, hide in conference rooms, work from home, or do whatever it takes to focus. In addition, indulge in lots of formal and informal brainstorming sessions with various members of the team such as the architects, principle designers, other senior verification engineers, software/firmware engineers, and even marketing personnel. During these discussions, don’t let the other person drag you into the ‘how’ or any other logistical issue like schedules or resources. Also note that everyone will be providing you their perspective based on their roles/background. I call these Swiss cheese slices; all will have holes, but stacked on top of each other will give you a solid list of cases.  

Lastly, start organizing this list hierarchically and in sections. Typically, there will be following sections:  

• Architectural or black box cases
  • eg, Read a sector from SATA interface with the interrupt enabled. In the Interrupt Service Routine (ISR), examine the contents of the sector read and clear the interrupt.
• Software or use cases
  • eg, The boot sequence; Bus enumeration sequence for the USB port
• Micro-architectural or Design cases (aka white box)
  • eg, state machine interactions; buffer full/empty conditions
• Block/sub-block level
  • eg, USB Link block level: Rest of the chip can be substituted by a Bus Functional Model (BFM)
• Cluster or System level interactions
  • eg, System Memory coherency and interactions with multiple requestors
• Compliance
  • eg, SATA, USB standards Compliance for interoperability;
• Error cases
  • eg, SATA Device sends erroneous packets
• Performance
  • eg, Memory Bandwidth  

Example of a hierarchy:  

• Major Feature: eg. USB packet Transfer types
  • Minor Feature: eg. Bulk Transfer
    • Test Scenario or a Test Matrix: eg. Minimum and Maximum size Bulk OUT transfers

In addition to writing down the test scenario, it is extremely important to note down any assumptions or questions one might have.  

A Generic Block

Let’s create a generic block to illustrate the process of identifying thorough top-down test scenarios:  

Generic Test Block

This block has several input and output data ports. There is a separate interface to access control/status registers. There are two clock domains and internal memory for local storage. In addition, there are some side band signals, along with several asynchronous events coming into the block such as reset, clock disable, mode control signal and so on. As an exercise, try mapping any blocks or designs you have worked in the past into this – you will be amazed! Make it even more interesting – map a microprocessor into this block!  

First order Test Scenarios for this generic block:  

• Access to all control/status register
• Access to all memory elements (both via standard datapath, and any special backdoor access)
• Complete protocol testing of all input and output interfaces (control and datapath)
• Exhaustive/interesting testing of all control logic (first order and ‘interesting’ register coverage)
• Exhaustive/interesting testing of any data computation performed in the block
• All possible/useful combinations of the two clocks
• Side band signal functionality
• All asynchronous events crossed with each other and skewed against each other
• All asynchronous events during ‘important or interesting’ states  of the block
• Memory element access during operations – corner cases (buffer full, empty)
• Stalling
• Hard and soft reset behavior
• Power management cases
• Performance

We just saw the ‘science’ portion of test-planning! Generating a robust first order list of scenarios for any block should be possible by going through the above exercise. This starts becoming an ‘art’ (or the intellectual process), once we start creating second order or combination tests; in short, the optimization process.  

Priorities

Now that we have a list of ‘all’ cases that need to be tested or covered, next thing to do is to prioritize them according to the importance. This can be used throughout the project to make tough schedule related calls. The priority should also be used to generate weighted coverage numbers.  

What is the basis of the priorities or the importance? The following set will serve as a useful guideline:  

• Atomic hardware functions that cannot be worked around using software. For Instance, basic addition instruction in a microprocessor
• Advertised features or normal operation of the machine are more important than others
• Any bug that can cause a catastrophic failure in the normal operation of the machine.

Another pragmatic view point is ‘assuming worst case scenarios’ – let’s say a bug that slips affects the reset or the boot sequence – this chip will be DOA (Dead on Arrival) – no bring-up or characterization can be done on this chip. Instead, say, the access to certain memory locations don’t work – this is definitely not something to be proud of, but, on the positive side, at least the operations of the chip using the lower memory locations can be tested out (including the development of the software). Thus, one would put the boot sequence test at a higher priority compared to the access to the entire memory range. Again, note, this example was just to illustrate relative priorities. Any verification plan that does not cover access to the entire memory map is indeed a very poor one!  

Note that this was just to illustrate how one can go about the prioritizing. There are a lot more factors that need to be considered for prioritizing that depends on your project goals.  

Reviews

We have identified, documented and prioritized all the test-cases (the ‘what’ portion). It’s time for a formal review. Very important to note – DO NOT WAIT to complete identifying and documenting all the cases before calling a review. As we all know, verification is an NP complete problem, and thus, one can never say that their plan is theoretically complete! Use judgment, and call the review once the plan is at, say, 90% mark. Some useful guidelines for the review:  

• Circulate the review material well in advance so that the audience has a chance to study it.
• No lengthy text or narration.
• Walk through the cases hierarchically (breadth first)
• Use appropriate visual forms such as tables, lists, pictures (remember, a picture is worth a 1000 words)
• Start with a block diagram and a description of the DUT ‘in your own words’
• Required Audience: Design counterparts, architects, and senior design/verification members, owners of adjacent blocks, owners of central blocks, software/firmware engineers, System/board designers and Managers.
• Have your manager or colleague collect action items.
• Don’t let anyone hijack the meeting. Keep it under your control – it’s your meeting.
• Call extension meetings if all the material cannot be covered in one session.
• Solicit feedback on the ‘priority settings’.
• Follow up on all action items and send the updated plan once all the action items are completed.
• Don’t get into the ‘how portion’ (or don’t let any drag you into the implementation) – Cover that topic in a separate review.  

The ‘how’ Portion

Now that all the cases that need to be covered are completely documented and reviewed, let’s look at the ‘how’ part. This part will determine or form the specification for the test-bench.  

The first order of classification will be based on whether something is tested using simulation, formal method or emulation.  Simulation provides more controllability and observability. This makes it easier and more practical to hit white-box cases. Also, debugging is much harder on the emulator. You don’t want to be exposed to first order bugs in the basic operation during the emulation. In fact, simulation based testing needs to be used as a screen before starting the emulation.  

Within simulation the scope of the DUT is the other decision point. Most of the cases intrinsic to a block should be tested at a block level. This makes simulations faster, debugging quicker and test setups easier. Also, during earlier phases of the project, all the adjacent blocks may not be developed or stable for cluster or system level testing.  

Formal method or tools are still limited in terms of ability. These are best suited for smaller blocks that are well specified.  

Cases that need a large number of cycles are best suited for emulation. Other types of cases suited for emulation or prototyping are the ones that test interoperability with real-life interfaces or devices such as SATA or USB, in our example.  

To summarize, here are some of the key factors influencing the testing method:  

• Debug-ability: Areas most likely to have lots of bugs. This is true for normal machine operation during initial phases of verification (fresh RTL code).
• Cases hard to control: error cases, multiple events happening at precise points
• Cycles needed to setup and exercise the case
• Requirement of real life devices to provide the stimulus/response(interoperability)
• Testing speed (some cases need at-speed testing)
• Number of theoretical cases. Some scenarios can explode – and there may be an opportunity to use formal methods to cover such scenarios  

Another practical tip here is to put greater emphasis on debugging ease and simulation times/turn times during the high bug phase, for instance, when there is fresh RTL code.  There is no need to worry about phases or cases where the probability or likelihood of hitting a bug is very low.  

Notes:  

• The test-bench and the test cases should be design in such a way that most or majority of the tests at a lower scope can be reused at a higher level.  Block level cases should be reusable at cluster level, and system level simulation cases should be reusable on emulators. This provides two benefits: the lower level or scope tests can be used as a screen to start testing at the higher level, thereby eliminating any build or database coherency issues. Secondly, the test setup knowledge at lower levels can be used at higher levels. For instance, for system level test cases, one should not be required to understand detailed setup up procedures of a SATA transfer in the context of the SATA Link when it has already been put in place at a lower level test-bench.
• Lastly, apply the 80-20 rule for test-bench designs. That is 80% (read as majority) of cases should be supported by the mainstream test-bench. For the remaining 20% (read as minority), a special ability or a hook needs to be added to the test-bench. Again, apply the 80-20 rule for this remaining 20% and keep going till all cases are covered. This will be reviewed again, and in greater detail, with examples in a future article covering test-bench designs.  

Coverage Measurement/Key Indicators/Metrics

Once the test-plan has been filled with all the test cases (or coverage scenarios) along with the priorities and testing methods, one can start creating various indicators and metrics.  

A single number providing the state of the verification program is always desirable. However, it is important to build this in a hierarchical fashion. This way, one gets to look at the coverage at various granularities such as block based, feature based, scope based and so on. This helps to make tactical project decisions.  In the final section we will look at how all of this data can be organized and consumed.  

The most popular methods of measuring coverage are:  

• Code coverage – toggle, block, condition, state machine, expression.
  This is the easiest way to generate coverage information. It is built into most simulators these days and can be turned ON or OFF with the flick of a switch.
  The advantages of code coverage are the ease of use, and detection of any first order hole. On the down side, it doesn’t quite tell us if we are done. Any ‘missing’ RTL code cannot be detected. Also, the coverage information is mostly combinatorial in nature. Sequential cases don’t get measured. Lastly, dead logic or architecturally irrelevant cases provide false negatives. 
  It is a necessary but not a sufficient condition. Lastly, code coverage monitoring in the mid-phase of the project is a good way to track project progress.
• Functional coverage:
  One of the things that code coverage doesn’t provide is a coverage view abstracted at a higher level. For instance, one will get information about whether all the bits toggled on the address bus, but it will not tell us if all ‘regions’ of the memory were accessed by a particular memory master. This kind of abstracted coverage information starts tying closely with the desired functionality of a particular block. In most of the modern HVLs (Hardware Verification Languages), one can easily instrument these ‘coverage points’ or ‘coverage buckets’ to provide an abstracted view of the coverage. This is the most effective way to track coverage, provided test-benches are developed using HVLs.
• Assertion Based Coverage:
  This is a form of functional coverage.  There are several assertion languages and libraries that one can choose from. Interesting cases can be coded as assertions and the simulator can then ‘watch’ for these assertions during simulations. Note, one can construct very ‘smart’ sequential or ‘temporal’ assertion, and tie these closely to the coverage-plan/test-plan.
• Register Coverage:
  This is a special type of functional coverage. Covering all the bits or knobs that control a particular block’s behavior can provide very useful first order coverage. One can then create combinations of various fields to cover interesting cases.  

Knowing or deciding ‘what’ needs to be measured and setting goals is more of an art than science. This is the intellectual exercise. Let’s take a block with 20 control bits or knobs. If you let a coverage tool measure the coverage on this without any constraints, it will look for all permutations and combinations of these bits or fields – that’s more than a million cases and most of the cases may be useless or irrelevant. Identifying or selecting ‘interesting’ cases is indeed an intellectual exercise. How good someone is in doing this will determine the efficiency and robustness of the verification project.  

Another way to reduce the coverage set or optimize it without risk is to look at orthogonal cases, based on the design and usage. For instance, one may never use two features or blocks of the design simultaneously – say, SATA and the Memory Card interface will never be in a product together. This can be used to drastically reduce the number of test cases. Note, that this can be dangerous if used without proper care. First of all, this has to be documented very clearly. Even better, make it a requirement that such cases need to be officially accepted by the program management.  

Test-Plan Management System

Last but not the least is how do we manage all this data? There is a lot of important data that needs to be created, stored and accessed with different views. Traditional ‘Word’ or even Excel based test-plans are not enough. These are not ‘executable’, hard to keep coherent with the test-base. Oftentimes, the testplan document never gets updated once it is reviewed, and by the end of the project it is almost obsolete!  

The real solution is to create a database for all the information, similar to bug databases. There are several solutions available in the market. Cadence’s VManager™ or Mentor’s ReqTracer™ are some of the examples. Jasper DA offers a freeware named Gameplan ™. Or, one can develop an in-house tool to manage the test-plans. Let’s look at how we might want to organize and access this data.  

Key factors to keep in mind:  

• Ease of use.  Anything complex becomes a deterrent.
•  Test-plan is a live document – keeps getting updated whenever new ideas prop up, and everyone ought to be viewing the most recent version
• Ability for different views
• Marrying the scenarios with simulation or implementation data
• Ability to tightly couple with the testbench collateral
• Track specification/design changes seamlessly
• Removing any room for ‘oops’ through automation
• Query based access
• Using test-plan to manage status information including coverage data.

Records

The atomic record in this database is a test case (or a test scenario). Some of the important fields are:  

• Summary and description field,
•  Module, feature, sub-feature
• Owner
• Test-case submitter (there may be a situation that someone other than the block owner thinks of a case)
• Testing Method(s) used: simulation/emulation/formal
• Scope(s): Block/Cluster/System
• Priority/Weight
• Test(s) that will cover this scenario
• Assumptions/Questions associated
• Coverage measurement method
• Status (based on back-annotated simulation data)
• Tags:  This can be used for queries to build different types of ‘test-lists’ or ‘regression lists’ based on the need.
• Simulation directives

Of course, once you start thinking down this route, there may be other attributes that you can use to make the system even more efficient for your environment.  

Access

Various access points are desired for proper use of this data. Some of these are:  

• Easy to use GUI based system to enter test cases, one at a time
• Importing (from, say, an excel spreadsheet)
• Backdoor access for simulation scripts (query based)
• Exporting into standard formats such as excel (query based)
• Back annotation of results and other status information
• Reporting – html or other forms based on queries (for reviews)
• Metric reporting in a tabular or graphical form (query based) 

So, we have seen the art and science behind creation of test-plans/coverage plans. Test/coverage plan development is a very creative process. To begin with, one needs to have an in-depth knowledge of the DUT being implemented. The ‘hunch’ is a cumulative knowledge of the protocols involved, usage perspective including the use-cases, intent of  the features, design methods used, historical perspective (knowing USB1.0,2.0 while testing 3.0), knowing where the bugs lie. The ‘hunch’ then allows one to prioritize, shortlist ‘interesting cases’. This allows crafting of the next ‘killer’ test case. However, this alone is not enough. Verification is as much about discipline. One might catch all the killer corner cases in a DUT, but completely overlook an entire section! Cases like these are not uncommon. Having a disciplined systematic approach in combing through all the possible test scenarios is a must. This is the ‘science’ behind verification test planning.  

In the next article, we will focus on test-bench design – on how to build robust and reusable test-benches. You might have the best or most exhaustive test-plan, but a poor test-bench can be a project killer.

About the Author:  Suhas Belgal has 17 plus years of experience in Chip Design, Emulation, Modeling and Verification, including 9 years as a Verification Manager. During these years, Suhas has worked for several multi-billion dollar companies such as Intel , LSI, Mentor Graphics, and various start ups, and co-founded a Verification Services company. Over the years, Suhas has played key roles several high profile design teams such as Pentium II, and successfully led several SoC chips to production.  He has experience in a wide range of Verification Methods and tools, and has been a presenter and panel member at various conferences, including the DAC. He has a master’s degree in EE from University of Texas at Austin and a bachelor’s from VJTI, Mumbai.

What: Panel discussion on Future Devices and Convergence as a part of InCSIghts 2010 organized by Computer Society of India, Pune Chapter
When: Saturday, 27th March 2010, 2:00 pm to 3:30 pm.
Where: Suman Mulgaonkar Auditorium, ICC Towers, Senapati Bapat Road, Pune 411016
Registration and fees: This is a paid event. Registration is required.

About InCSIghts:

InCSIghts is the annual CSI IT roundup and will be held this year on March 27, 2010. The event will showcase a broad range of topics that IT professionals and academicians shouldn’t miss.

This event will try to give audiences a sneak peek into technologies that will dominate the future and analyze their impact on IT professionals. It will also focus on issues relevant to industry needs today, both business and technical. InCSIghts is Pune’s premier annual event that delivers an informative and actionable perspective of the issues shaping our industry with a peek at the future of technology. This year, InCSIghts brings you some of the most respected names on Pune’s IT scene with a cuisine of thought-provoking items on the agenda.

We have planned four sessions this year – Technology, e-Governance, Computer Science Research and Future of Mobile Devices and Convergence. Here are details:

Future of Devices and Convergence:

A new breed of mobile devices that offer tremendous productivity boost to the average user is just around the corner. As we are just starting to get used to the ubiquity of constantly connected mobile smart phones, future mobile devices promise a significantly enhanced feature set over the existing ones. Devices such as the iPad from Apple, Kindle from Amazon or the Adam from Notion Ink are some examples that highlight this new trend.

These advances bring new challenges to the software development community which has hitherto been focused on programming for personal computers. It is quite obvious that the software developers must embrace new trends in order to survive and prosper. This panel discussion is the ideal setting to start the conversation between the hardware makers and the software developers, as the focus of the discussion will be on various technologies/platforms/form-factors that will be prevalent in newer devices. The attendees can expect a spirited discussion on the following topics:

1) Awareness of current and future technologies/platforms/form-factors

2) Consideration on power, usability, ubiquity which are not that important in PC programming

3) Programming platforms and programming tools

4) Marketing your software product

5) Considerations for building the hardware

Contact:

Please write to:  info.csipune@gmail.com

FPGA as the PCB's Grand Central Station

Earlier this week, Cadence Design Systems acquired an EDA startup, Taray, Inc. Financial terms were not disclosed.

This is important because it is an Indian EDA product company story.  While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.

Nagesh Gupta, Taray’s CEO said, “This was an inspiring innovation done right from India. The technology, which includes two issued patents and one pending patent was developed entirely in Hyderabad.”

Nagesh Chillin' in California

Cadence is one of the big three EDA players in the world, or three and a half, if you count Magma. Cadence is very good at the ASIC design flow, however, their FPGA design flow is lacking. With the Synopsys acquisition of Synplicity last year, they were certainly playing catch-up. Taray’s product called 7Circuits fills a gap in their FPGA PCB co-design flow. Cadence had already signed an OEM deal with Taray last year and the question was not if, but really when the acquisition would happen. 7Circuits is an FPGA I/O Synthesis tool.  As all FPGAs are re-prgrammable, the IO assignments change every time you make a design revision. This is a significant problem if your PCB is already in production. As more and more FPGAs with thousands of pins are now hitting the market, an intelligent tool like 7Circuits is absolutely required to do this job. You can read all about 7Circuits here.

Why was Taray successful in making this happen? There are three major reasons. First, they identified a niche area where no current solution existed. Gupta has a very strong system design experience, and this was a problem that he personally had faced many times. Customers were using home made scripts and excel sheets to solve the problem. 7Circuits is not only easy to use, but delivers significantly better quality of results over current methods.  Secondly, Cadence was the perfect suitor. They had a weak FPGA product line, while the competition had better tools. Third, FPGAs are getting bigger and faster all the time, putting pressure on I/O. This trend will continue for a while as 40nm products have started shipping and 28nm is just around the corner. With advances in the lithography technologies, we may even see a dip below sub-micron geometries in the future. Looking at the growing FPGA market, Cadence can easily add $5m – $10m to their bottomline if they use the right pricing and selling strategies.

Indian EDA companies can indeed take heart from this, but they need to make sure that they are addressing the right market.  The mainstream EDA business is a mature business. As number of ASIC design starts continue to decline year over year, the market for super expensive, super complex design tools is dwindling; obviously there are fewer seats that can be sold every year. Plus, severe cost cuts at chip design houses mean lower budgets and lower margins for EDA tools. Focusing on the FPGA market makes a lot of sense as that is the only market that is growing in size. FPGA ASP has been rapidly falling in the last ten years meaning that the chips are much more affordable; something that was not true just a few years back. What this does is increase the number of designers working on FPGA based systems. By some counts, there are over 100,000 distinct FPGA customers not including smaller ones who buy from resellers. Compare this to tens or maybe just over a hundred chip designers and manufacturers. The only problem with FPGA houses is that they are used to free or cheap tools; they have been spoiled by the FPGA vendors who often offer free or really cheap software. That said, they always buy tools that have a compelling value to them.

The lesson learnt here is that rather than concentrating efforts on the ASIC design flow, look at the FPGA design flow and find niches that you can easily fill. The answer is going to be simpler and far easier to reach, especially from India. Secondly, do not try to price your products like the mainstream EDA vendors. If your tools incorporate a must-have feature set and are priced within reach of the average FPGA design house, they will sell. Remember, you are looking at hundreds of thousands of license in total, not a few hundred. After all, there is a fortune to made at the bottom of the pyramid. Lastly, work on your sales and marketing process. If you have tool chains that cost just a few hundred dollars, it is very likely that you can successfully use the internet to sell and market your tools and avoid the traditional rep – distributor model. As examples, signal integrity tools, DSP tools, embedded processing tools that just work only with the FPGAs are likely to be big markets as buying licenses from Mentor Graphics, or Mathworks, or Windriver is often out of reach of the average buyer.

photo credit: stars6 / Leonardo Rizzi

On January 15, 2010, LSI hosted its Datacenter Evolution 3.0 forum in Pune. The Pune center is certainly getting a lot of prominence within LSI as the top two LSI execs, Abhi Talwalkar, CEO and Jeff Richardson, EVP Semiconductor Solutions Group, were hobnobbing with the attendees. VP and LSI India MD, Pravin Desale was the EmCee. Talwalkar has a strong personal connection to Pune – he was born here! He has presided over a complete makeover of the company where all internal manufacturing has been completely eliminated. LSI now is a silicon, systems and software Technology Company playing in the Storage and Networking verticals. Obviously, datacenters are a very important market.

Robinson, in his keynote, talked about how datacenters need to evolve to support the upcoming surge in data and traffic (Figure 1).

Figure 1: Surging Internet Traffic and Data; Source: LSI

His take is that new datacenters need to satisfy three key requirements – manageability, scalability and green-ness. A couple of technological innovations are powering the drive to the management and scaling of datacenters; an application aware infrastructure and storage device performance. There are also a number of innovations that reduce datacenter power consumption at all levels from device to software.

Application Aware Infrastructure

Initially, all network traffic was treated the same way, essentially as an Ethernet packet. That, however created a problem where higher priority traffic was often bottlenecked. In addition, there is no way to confirm a packet’s bona fides. The solution to this problem lies in inspecting the packet before it is forwarded to its destination. DPI or deep packet inspection technique allows looking inside a packet to identify what application it belongs to such as e-mail, VoIP, Video, HTTP, etc. and whether the packet is a virus or malware. Application awareness (Figure 2) allows infrastructure devices to meet the quality of service (QoS) requirements of the application along the entire path. With the pending move to cloud computing, application awareness is required to provide consistent performance at all points.

Figure 2: Application Aware Infrastructure; Source: LSI

An application aware infrastructure has better performance, much better levels of security and control and better management of resources. Networking giants such as Cisco Systems and Juniper Networks already use DPI in their latest generation network processors and a number of supporting devices are also hitting the market.

LSI demonstrated their Application Recognition Products at the event. It turns out that the entire development has been done by the LSI networking team in Pune.

As with any technological advance, there is a dark side; a rogue installation could use DPI to exploit an application vulnerability and to mount attacks. DPI can become a tool for govt. bodies to spy on its citizens or for organizations such as RIAA or MPAA in their overzealous attempts to fight piracy. Rumor has it that the Chinese govt. is very interested in DPI. As such, DPI vendors will need to work together with application developers to provide fool proof security to users.

Device Performance

As Ethernet speeds move from 10G to 40G/100G, an inflection point in storage device performance has been reached. SSDs or Solid State Drives offer 1000x input/output operations per second or IOPs when compared to hard disk drives or HDDs. While performance is high, SSD overhead cannot be hidden in RAID stack as you can with HDD. SSD cost is also an issue, and as such HDDs currently rule when high-capacity storage is required, but that advantage should go away once SSD volumes improve. In the current scenario, a hybrid storage that uses SSD for cache and HDD for main storage is certainly something worth looking at. The area where HDDs are expected to have a major advantage is where a large number of small files need to be stored, but that is something that could be worked around by application providers.

Here’s a recent performance comparison of SSD vs HDD performed by Tom’s Hardware.

As internet traffic and data are expected to grow by leaps and bounds in the coming years, it could be just that the next rounds of datacenter evolution (4.0, 5.0, …) may just be round the corner.

 image credit: Alessio Damato

This is a PuneChips event, a forum for Pune people interested in semiconductors design/apps/EDA.

What: Talk by Ganesh Bhokare on Wavelet Transform & its Applications in Image Processing   
When: Saturday, 6th March 2010, 10:00 am to 12:00 noon.   
Where: Venture Center, NCL Innovation Park, Pashan Road       
Registration and fees: This event is *FREE* for all to attend. No registration required.

Wavelet Transform & its Applications in Image Processing
In today’s multimedia wireless communication , major issue is bandwidth needed to satisfy real time transmission of audio and video data. The solution to this problem is to efficiently compress audio and video data for a given SNR. Wavelet transform is an evolving technology which offers far higher degrees of data compression compared to standard transforms such as DCT etc. In this talk we will be discussing concepts of wavelet transform and its applications to image compression and processing. The same can be extended to video processing.

About the speaker – Ganesh Bhokare   
Ganesh Bhokare has over 15 years experience in using DSP audio, video and Embedded systems for Digital Media Processing. He is a PhD candidate at IIT Mumbai and currently in the process of defending his thesis. He has professional experience with  NXP, Conexant, TI and Cirrus Logic.

About Venture Center   
Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.     

About PuneChips   
PuneChips is a special interest group on semiconductor design and applications. PuneChips was formed to foster an environment for growth of companies in the semiconductor design and applications segment in the Pune area. Our goal is to build an ecosystem similar to PuneTech for companies in this field, where they can exchange information, consult with experts, and start and grow their businesses.        

For more information, see the PuneChips website at http://punechips.com, and/or join the PuneChips mailing list: http://groups.google.com/group/punechips.  Please forward this mail to anybody in Pune who is interested in renewable energy, solar technologies, semiconductors, chip design, VLSI design, chip testing, and embedded applications.

This is the first in a series of blogs written for PuneChips by Suhas Belgal titled Field Manual for Verification Planning. The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.     

The objective of this series is to provide a view of the ‘art’ of design verification. Everyone has heard the quote “Verification is an NP complete problem – it can never be done”.  If so, how should one schedule the verification program? When is the chip really verification clear for tape-out or production? If it is art, how does one measure the quality? Or, how does one turn it into ‘science’ and bring predictability into the equation?  Recently, while reading Robert Pirsig’s famous book “Zen and the art of Motorcycle Maintenance”, the questions of ‘art’, ‘science’ and ‘quality’ of the chip being designed crossed my mind…This series will provide a practical insight into the various aspects of verification, different tools, methodologies, best known practices, key indicators, tracking and management while trying to reflect on the fundamental question of whether verification can be completed. All of these will help bringing in the much needed predictability into the verification program. However, all of the best know practices and automation tools in the world can still not replace the need for engineering intelligence. You still need the best and the brightest minds to tackle the challenges. On the flip side, this is what makes verification challenging and interesting, and will attract the best minds out there. So, sprinkled throughout this series, you will find the term ‘intellectual process’ or ‘intellectual exercise’; the part of the process which still needs human intelligence or an engineering discretion will be identified as the intellectual process or the intellectual exercise.The basic goal of any chip design verification project is to find ‘all’ the bugs before tape-out! One way to bring pragmatism is to clearly identify the context of the statement of bug free design. That is, the design should be bug free for a crisply identified goal such as ‘customer demo/samples’ or ‘to enable software development’.  Even with such constraints, it still remains to be an NP complete problem. This is where statistics, probability can come in, and various indicators can be used to define the verification quality.          

In addition to the fundamental goal, there are other objectives such as productivity, efficiency, resource usage, ‘finding critical bugs earlier’ and so on. These are as important, as a matter of fact, even more important oftentimes than the basic question of ‘have we caught all the bugs’.     

Basic Dimensions   

The three basic dimensions of verification are ‘Coverage’, ‘Stimulus’ and ‘Checker’. Regardless of the tools or methodology, any verification environment consists of these three parts.       

Coverage addresses the fundamental question of how complete the verification is. This being an NP complete problem can never be complete, theoretically. However, in reality, setting the ‘denominator’ of the ratio – ‘covered vs planned’, becomes an intellectual exercise. Certain practices and pitfalls will be covered in detail in the ‘coverage/testplan’ topic.      

Stimulus can be deterministic, but can explode very quickly. Say, a 2 input functional block can be covered exhaustively in 4 cases. But, a 256 input block will require  1.1579….e+77 combinations – impractical! Even worse, sequential elements add a time dimension. Finding proper methods to select or prioritize ‘important’ or ‘high leverage’ stimulus is an intellectual exercise.       

Checker or rather, not having a thorough checker will make the two other dimensions useless. One can have a ‘complete’ checker only if the definition of that the expected behavior is complete. Usually, this is covered by the Design or the Architecture Specification of the chip or the product. Proper interpretation and checking for completeness is an intellectual process.     

Flow/Process  

A typical flow involves the following steps/phases, interspersed with reviews (every phase should begin and end with reviews).       

1. Design/Specification study
2. Coverage planning (traditionally known as test-plan development)
3. Testbench design planning
4. Setting up the Verification Environment – databases, bug tracker, templates, regression/simulation environment, debug process, indicator tracking
5. Testbench implementation
6. Coverage plan implementation
7. Bringup (fresh RTL tested against fresh testbench)
8. Feature coverage
9. Coverage exploration
10. Final Checklist

Verification Methods  

Several methods can be employed to carry out pre-silicon verification. The primary being Simulation based, Emulation based and the Formal method. All have pros and cons and can be used to complement each other.       

Simulation method utilizes dynamic simulation techniques used at different scopes such as ‘module or block’ level, ‘cluster’ level or the ‘full chip’ level.  Lower granularity helps speed up simulations, catch basic bugs quickly.  However, cluster or full chip environments help check the interactions between the blocks, which are a common source of bugs. However, at higher levels, simulation speed slows down, and one starts encountering ‘controllability/observability ’ problems.       

Emulation, hardware acceleration, proto-typing allows testing at much higher speed, and possibly at-speed.  Hardware/software co-verification, using real life devices can be accomplished using emulators.  Primary advantage is to get large number of cycles needed reach certain states of the design, say testing thousands of HD video frames. Also, one can actually bring-up peripheral devices such as SATA hard drives, thus taking out any risk in the implementation. Downsides are the cost and debug ability.       

Formal methods prove behavior of a certain section of the design to match a certain set of properties mathematically. Thus, it’s exhaustive and complete! However, there are logistical limitations to the current generation of tools such as design size, speed, and even then, coverage is still only as good as the property set. Defining the property set is an intellectual process.     

Productivity  

Productivity or the efficiency pertains to the processes, environment, tools, methods which can improve the verification cycle. The major costs are the ‘direct’ $ cost, human power cost and the cost in terms of total calendar time.  Simulators, emulators, server farms, other tools contribute to the direct $ cost. Calendar time is the critical path, and accounts for the processes that cannot be temporally scaled.       

Buy vs. brew is always an important decision, and comes across multiple times during a project. The maintenance cost of developing a tool in-house should not be ignored while making this decision.       

The non-deterministic, open-ended nature of verification complicates resource planning too. Predicting the number of simulation licenses needed, server farm size/capacity and estimating the total cycles needed to flush out ‘all the bugs’ is an intellectual process.       

Simulation license usage, cycles, build times, run-times need to be tracked before they can be improved. Scripts/tools to track these indicators should be planned for. In addition, the bug tracking (rate of opening/closing bugs, turnaround times etc), rate of test development, coverage improvement needs to be constantly measured for improvement.     

Environment   

Verification Environment is a key part of the verification project. This includes organizing the verification collateral, selecting an efficient and robust revision control system, work flow, automation to avoid manual mistakes and improve efficiency, integration of various pieces of verification and choosing an efficient platform for the entire team, including designers, to develop complex projects. And, in today’s global development community, an efficient environment is the key to success. Groups can be spread all over the world, but their development environment should be identical or seamless.       

Discipline and attention to detail are extremely important. How many times have we heard or experienced cases where bugs have slipped through the cracks in spite of having a ‘test’ that should have caught them – just because the test was not run on the final version of the netlist, or the test was not a part of a certain regression list. These mistakes are expensive, to say the least. Adding mere stress and pressure on engineers doesn’t help either. A fool-proof process and a set of tools/scripts can mitigate these circumstances.     

Verification Language    

The biggest wars in the verification world are on this topic. The modeling language for creating test-bench and the tests is central to any verification strategy. Starting with a bit of a historical perspective, Verilog or VHDL have been traditionally used for verification along with design. The ‘behavioral’ constructs in these languages aid verification tasks. Even today, several companies/projects rely on verification strategies based entirely on Verilog or VHDL. Using Verilog or VHDL has its advantages; the language knowledge is universal, no special simulators are needed, and most of the EDA tools understand and support these languages. On the downside, these languages were primarily designed to describe digital circuits/logic. They don’t have powerful data structure constructs. Randomization support is very limited.       

To circumvent these limitations, common powerful languages/scripts such as C and Perl have been introduced. C or Perl provide the language or programming power. However, they are still not specifically ‘verification languages’, and every project/company tend to have their own implementation of the methodology.       

Over 10 years ago, a new breed of specialized languages known as ‘Hardware Verification Languages (HVL)’ came into existence, starting with Vera and Specman. Vera was born inside Sun Microsystems as an internal verification language/tool. This was spun off and eventually became part of Synopsys. Most recently, the industry trend has been towards SystemVerilog, in an effort to standardize on the language.  HVLs provide strong Object Oriented Structure and advanced features for randomization and constraint solving. In addition, they have become platforms for myriad of verification functions such as coverage monitoring, assertions and so on.      

Finally, the most recent development has been that of a methodology layer via libraries. VMM, OVM are the two main methodologies in the market today for System Verilog.      

One could argue that everything that is provided by these higher level HVLs or the libraries can be implemented in Verilog or VHDL. True! But, firstly you get a tremendous boost in productivity as these libraries or languages provide a high number of pre-defined functions, constructs. Secondly, these libraries provide a framework that inherently makes the collateral reusable and efficient.        

Random, Directed, Emulation?     

Another contentious area for design and verification teams is to decide between random, constrained random or directed testing. Another dimension of this debate is the simulation vs. emulation decision. The pros and cons will be discussed in detail in a future article of this series.        

Sometimes, it helps using analogues. For instance, how would one test out a car – would one use a test-track with ‘simulated’ skids, obstacles and other external environmental factors, or just drive 100K miles on an expressway. One could use this analogy further and even look at orthogonals – say, if the blinkers have been tested in the garage, is it necessary to test them while driving through winding hilly roads, or say, while driving through winding hilly roads while the outside temperature is sub zero and at night. This helps reduce the set of interesting test cases.      

Reviews/Checklist    

As mentioned earlier, discipline is very important in Verification. Verification is the final safety net prior to tape-out. Any hole can potentially cost millions. In addition to inserting checks and balances into the tools/scripts/processes, reviews and checklists have a significant role in any verification project.        

For reviews, key things to understand are:      

• Primary intent should be to solicit feedback from other team members. Thus, every attempt should be made to communicate the content clearly to the attendees. A good idea or a clarification or detection of an error can save lots of time, frustration downstream.
• Put as many figures, tables as possible. Avoid textual paragraphs. A picture is worth 1000 words!
• Example code review is highly recommended.
• Time should be used efficiently but one should not limit wall-clock times     

Some of the useful review/checklists, other than the usual, are:      

• Tape-out checklist. Some of the items are
  • Waived coverage points or tests along with justification
  • Waived bugs along with justification
  • Uncovered planned items, if any, with justification/risk assessment
  • ‘What-else’ checklist: Once all the planned verification activities are completed along with a satisfactory bug curve, a series of what else reviews are recommended. This is a free flowing brainstorming of what else can possibly be done to find the bugs. As we all know, all bugs can never be found – which also means there are always more bugs in the design to be found and these reviews can potentially lead to them.
  • ‘Last set of bugs’ – (This category or the review needs a better name!): Towards the end, around the time the ‘what-else’ reviews are held, the last set of bugs uncovered should be reviewed or analyzed for the following:
    • What found the problem – was it accidental?
    • What caused the bug – did it exist all along or a recent event caused it?
    • Could it have been caught earlier?
    • What if it had slipped? Is there a workaround? This tells the severity of the bug    

These questions and discussions usually give rise to a few more clues or ideas about how to look for the remaining residual bugs.      

Modeling     

Modeling is a very generic term. In the context of verification, this is used for a ‘model’ that describes the correct or golden behavior. Often times, this arises out of architectural exploration efforts.        

Models can be developed in C (most common), MatLab, SystemC, SystemVerilog, and Verilog or for that matter, any language.        

When used as a golden model for verification purposes, it is very important to consider the verification requirements as this can have a very high impact on the productivity or efficiency of the project.  Most of the time, there are surprises, as the models are developed much before verification starts and/or by different groups. Avoid them by planning and collaborating ahead of time with the modeling team. Verifying these models independently is always an interesting and important problem.     

Performance Verification     

This being very important, requires explicit attention. Performance, as opposed to functional verification, can be tricky due to two things. Firstly, setting up cases or ‘checking mechanism’ is not covered by the traditional functional verification collateral – thus, it is more work and often comes as a surprise. Secondly, identifying, defining and quantifying performance metrics is non-trivial. For instance, if the specification identifies the startup time of, say, a product like an iPod to be less than 2 seconds, then one needs to identify functionality in the hardware that contributes to this delay and then use that number to check for correctness. Sometimes, ‘quality’ aspects are not clearly quantified – especially, the acceptable numbers. Video quality is a good example of this.      

Other Verification Areas     

While planning for verification, following areas or special cases need to be considered   

• Handling clock domain crossings
• Simulation artifacts, for instance, code that could mask propagation of Xs
• Design rule violations that will not be caught during traditional simulation/emulation
• Check for  potential errors introduced by the RTL -> GDS process
• Analog components, and their interface with the digital logic
• Process variations and the logic implemented to compensate, for instance, DLLs.
• Power simulations are going to be commonplace going forward

Example DUT     

Let’s take an example DUT – a simple SOC. We will throw in some standard SOC components – a host processor, a co-processor (such as a DSP or some such computational element), internal buses for both control and high speed data transfers, a memory sub-system (DDRs, SRAMs), peripheral IO interfaces such as USB, PCIe, UART, and internal SOC control elements such as IO muxes, clock/power management unit, interrupt management unit.       

The following block diagram illustrates our example. All the future topics in this series will be discussed in the context of this example. 

Example of a SoC DUT

Summary

Throughout this series, we will make an effort to identify the ‘art’ and ‘science’ involved in Chip verification, with practical tips or some of the best known practices. Through use of advanced techniques, tools, methods, discipline, best practices one can mitigate the non-deterministic nature of verification. These can be used for accurate scheduling, planning and a high quality execution of verification projects leading to successful first pass silicon. However, there is an ‘intellectual’ part of the process that still requires the best and the brightest minds.  And, that’s where the satisfaction or the intellectual rewards lie. Verification accounts for 70% of the pre-silicon development efforts, according to some estimates – let’s not leave it to chance by quoting the famous ‘verification is an NP complete problem’ – it can be harnessed and this has been already demonstrated by several successful groups, companies.       

In the next session, we will cover ‘test-plan/coverage plan’ topic in detail.       

About the Author:  Suhas Belgal has 17 plus years of experience in Chip Design, Emulation, Modeling and Verification, including 9 years as a Verification Manager. During these years, Suhas has worked for several multi-billion dollar companies such as Intel and LSI, various start ups, and co-founded a Verification Services company. Over the years, Suhas has played key roles several high profile design teams such as Pentium II, and successfully led several SoC chips to production.  He has experience in a wide range of Verification Methods and tools, and has been a presenter and panel member at various conferences, including the DAC. He has a master’s degree in EE from University of Texas at Austin and a bachelor’s from VJTI, Mumbai.      

This content has been licensed to PuneChips under a Creative Commons Attribution-Noncommercial 2.5 India License. Contact Suhas Belgal for details of how to attribute and re-use for non-commercial as well as commercial distribution.    

photo credit: david.nikonvscanon

This a joint event organized by PuneChips and IIT Bombay Alumni Association – Pune Chapter. PuneChips a forum for Pune people interested in semiconductors design/apps/EDA. For details see http://www.punechips.com

Please note the different timing. This event is on a Saturday at 10am at the same venue; NCL venture center
 
What: Talk by Dr. Madhu Atre: India – A Bright Solar Future 
When: Saturday, 16th January, 10am to 12pm.
Where: Venture Center, NCL Innovation Park, Pashan Road: http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/
Registration and fees: This event is FREE for all to attend. No registration required.

India – A Bright Solar Future
As global warming begins showing its bad side, it is important for everyone to harvest new and renewable sources of energy. Applied Material is and continues to be a pioneer in the field of solar energy. Madhu will talk about trends in solar technologies, viability, opportunities (especially software/services related) from an India perspective
 
About the speaker – Dr. Madhu Atre
Dr. Madhusudan V. Atre (Madhu) is the President & Managing Director of Applied Materials India. As the leader of the Applied Materials India management team, he is responsible for strategy and operations in India; and ensures alignment, coordination and execution of all product development, business, and operational activities.  Dr. Atre represents Applied Materials in India to the employees, customers, business partners, local and central government officials. He also provides executive leadership at all the India sites, and is the Applied Materials India legal representative. With over 24 years of experience in the semiconductor and computer industries after his PhD, Dr. Atre has also donned other technical, management and leadership roles – as the Vice President and Managing Director of LSI India, founding Managing Director and Vice President of Agere Systems India, founding director of Lucent Technologies Microelectronics Division, and several management positions at Texas Instruments India, and India’s Defence R&D Organization
 
Dr. Atre has published/authored more than 40 technical papers/articles in reputed journals/conferences, as well as thought leadership articles on semiconductor and solar industry; and also lectured in many technical and industry forums.  He holds a 5 year integrated M.Sc. degree in physics from the Indian Institute of Technology (IIT) Bombay, and a Ph.D. in theoretical physics from the Indian Institute of Science (IISc) Bangalore. He has been a research scientist at the Tata Institute of Fundamental Research (Mumbai), Physical Research Laboratory (Ahmedabad), and universities in the US and Italy.

About Venture Center
Entrepreneurship Development Center (Venture Center) – a CSIR initiative – is a not-for-profit company hosted by the National Chemical Laboratory, Pune. Venture Center strives to nucleate and nurture technology and knowledge-based enterprises by leveraging the scientific and engineering competencies of the institutions in the Pune region in India. The Venture Center is a technology business incubator specializing in technology enterprises offering products and services exploiting scientific expertise in the areas of materials, chemicals and biological sciences & engineering.

It is very clear that SystemVerilog is clearly targeted at improving designer productivity. Failing productivity due to increasing design complexity is one of the biggest challenges faced by chip designers today, and it is not at all surprising that the EDA tool industry is focused on rectifying this. The chart below (source: SEMATECH) shows a rather grim picture – while design complexity has been growing at 58% CAGR, productivity has been increasing at only 21% CAGR. It is obvious to anyone that tools that fill this gap will be in great demand.

The reason for increasing design complexity is multifold – decreasing geometries allow designers to add more and more elements to the chip, making the entire process challenging. Number of IP cores per chip has grown from ~30 in 2003 to over 250 in 2006 and possibly much more today (source: EETimes). In addition, a big bull’s eye has been painted on power consumption numbers and most chips now must be designed using low power techniques. Plus, increasing complexity means that chip verification becomes more complex; 50% of all ASIC designs today require respins due to functional/logic errors (Source: Colette International Research).

Rather than a single solution, it is very likely that a multitude of innovative solutions that address individual problems will emerge. For example, better modeling techniques that can give a very accurate QoR estimate at the architecture stage itself can reduce the design complexity downstream. Languages such as SystemVerilog literally reduce the lines of code that a designer or verification engineer must write, thus boosting productivity. Time also may be right for ESL design, which has been around for a while, as conventional techniques fail to keep up. 

All in all, we live in very interesting times. Faster and smaller is not always for the better. The industry must innovate and rise up to the economic and design challenges if it is to survive and prosper.

As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what.

ESL or Electronic System Level testing is the newest trend. Supporters of ESL claim that it is a highly powerful system level modeling tool. It enables fast software bring-up if combined with an emulation/FPGA prototyping platform. ESL has been used successfully to validate systems for mobile applications where only one peripheral/application is active on the processor bus. ESL does not seem suitable for systems where multiple processes and interfaces are active simultaneously, like for example in a networking system.

Formal verification, a static verification technique which is mainly assertion based, is useful to check control paths. It cannot be used to verify datapaths. Dynamic simulation is a very effective way of verifying functionality of every block in the ASIC including the datapath. Gate level simulations performed after the back annotated placement and routing data is available are used to identify timing related issues or omissions/errors in stating multi-cycle paths.

The need to find hardware bugs as early as possible in the ASIC lifecycle drives the emulation and/or FPGA prototyping effort. Both these techniques enable the testing of scenarios which are generally not possible to test in dynamic functional verification, well before the actual silicon comes back from the fab. Emulation or prototyping also accelerate fast software ramp up and the software team can get a development platform ready well before the actual chip is available. Emulation involves running test cases on hardware accelerated platforms like Palladium from Cadence and Veloce from Mentor. For FPGA prototyping, Single or multiple FPGAs are used to build a PCB system targeted for the testing of the ASIC/SoC. The ASIC code is then fully or partially programmed on the FPGA/s and functionality can thus be tested.

Scenarios with much longer simulation times than what normal functional simulation allows can be run on the emulation platforms. All the internal signals are available for viewing and debug, just like in functional simulation. The FPGA prototype platform does enable longer test time, but the debugging available is limited. The hardware accelerators are costly, and investing in them makes sense if a company has lot of ASIC programs running simultaneously. For companies which have similar chips planned back to back, investing in a home grown FPGA based emulation/prototyping platform makes sense. Another advantage FPGA prototyping is that the RTL goes through a complete synthesis and place and route cycle and testing is done on a circuit which is as close to the real ASIC as possible.

To ensure that a bug free product reaches the customer is a complex activity and poses multiple challenges. Coverage, legacy code, repeatability are issues that need to be tackled. Ensuring that the coverage is at an acceptable level is important. Code coverage is run to find out if all the possibilities of a written code are exercised in a test suite. Simulators from cadence (ius), synopsys(vcs) and mentor (modelsim) have their own code coverage analyzers. Functional coverage means to find out if each feature listed in the specification for an ASIC/SoC is verified. It is essential that the functional specification document has an individual numbered paragraph for each feature so that traceability is easier. Functional coverage is an activity that needs planning, reviews and careful test case designing. Methodologies like eRM (e reuse methodology – Specman based) and OVM (open verification methodology – System verilog based) do assist checking functional coverage, but the inputs provided need careful specification and reviews.

Reviews, not just for coverage, but at every stage in the ASIC cycle are extremely important. One of the challenges encountered while designing an ASIC is that the hardware team interprets a certain behavior from software and the software expects that certain things are taken care of in hardware. It is very important to involve members from design team, verification team, architecture team, software & firmware team for verification review.

It takes a good amount of effort to come up with a verification environment, and it is very common for a team to use what has worked before when schedules are demanding. Legacy environment saves lot of time, but it also handicaps the team. Talking about saving time, efficiency goes a long way in shrinking the schedules. The initial time and effort investment in automation of repetitive tasks save lot of time in future. Use of re-usable methodologies will definitely save time and effort.

Finally, while choosing the verification flow for a certain ASIC, team needs to look at what is available in terms of resources as well as time, understand the end user requirement, and make a decision on which technique to employ at what stage.

About the Author

Arati has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See her linked-in profile for more details.

So where does one begin? One good starting point may be with a popular indicator used to gauge the “goodness” of EDA tool’s output: “Quality of Results”, or QoR. QoR is used as a higher-level indicator of process quality, much like a Customer Satisfaction Index that up-levels feedback on specific aspects such as timely delivery and responsiveness. IC design EDA tools have used to showcase what they can do. So is it possible to expand its scope to include “greenness” as well? Or is it just an attempt to paint a turkey blue and pass it off as a peacock?

QoR is one of the long-lived and often-used keywords in Silicon Valley – surely on par with “information superhighway” in sheer citation count. Yet the latter phrase isn’t heard much anymore. It just reminds us of the 90’s internet boom, and doesn’t convey anything that is new today. After all, this superhighway is now as much part of our lives as electric power distribution is, and it has been a while since either created much excitement. And so is “QoR” similarly frozen in time as well, not staying up-to-date with today’s design challenges?

Let us take a quick look at how QoR has evolved over time. In the early days of IC design, the biggest challenge was to pack as many transistors onto a single die as possible. The self-fulfilling prophecy of Moore’s Law had setup expectations that somehow had to be met! And while the accompanying frequency spiral required lots of efforts to maintain, it was achievable. Thus the QoR directly reflected “transistor count” and “frequency” as the most important indicators of EDA tool capability. Other variations appeared, such as the packing density of logic and analog circuitry.

“Power” then appeared on the QoR scene, as limits of battery power and even socket power were approached by systems. Now EDA vendors could speak the language of the system architects with their “power-performance-area” optimization triangle. Higher-level performance metrics such as MIPS and FLOPS entered. Then came combinations such as “MIPS per megahertz per watt.” Thus the QoR definition expanded from the “micro” qualities to encompass the “macro”: from frequency and packing density to power and performance.

Looking at current trends in the economy, “Going Green” has taken on big importance everywhere. It is the socio-politically correct thing to do, regardless of your product or service. Companies with physical products joined the bandwagon early: building architects, automobile manufacturers, consumer electronics OEMs, and IC manufacturers. One software company that has made a start is Google, with its goal to “minimize its carbon footprint.” Other companies have been slower to adapt – maybe due to having “soft products,” or maybe because they find it hard to make the right connection into this trend. But the semiconductor industry and the EDA industry are inevitably subject to the same greening trend, and can not convincingly “opt out.”

But “Being Green” is as high-level a quality metric for an EDA product as any – so much so, that whether it even applies to EDA tools is sure to be hotly debated. Yet suppose, for a moment, that it were to be made a part of QoR, how do you think it can be done?

Initial thoughts that come to my mind suggest getting a “Green Process” certification for the EDA tool development cycle, analogous to the ISO9001 or CMMI certifications. In the future, such certifications could surely be applicable to any business or organization (maybe even an individual!), and the EDA industry would be no exception. Another possibility is to publish a “carbon footprint” or “carbon neutrality indicator.”

But the above “green indicators” apply only to the development of the EDA tools, and give no satisfactory indication of whether their use will lead to “green products”. My best suggestion so far to gauge that quality is to measure the tool performance (the fewer compute cycles it burns, the better) and its reuse (the more, the better). Reuse can be in terms of reusing the building blocks (within a project), the output (across projects) and even the hardware utilization (e.g. exploiting multicore architectures). I believe these quality measures will anyway be applied to the evaluation of EDA tools, because they also affect development cost and schedule. So one might as well explicitly go after these indicators and kill two birds in one stone!

On the downside of a green QoR, we could be chasing a red herring. Isn’t it be better to focus on the core job of the EDA tool, which is to make the design task easier? To what extent do we go in order to conform to this latest fad? And how about degrees of greenness, and who measures those? If two tool vendors claim to be green, how do I verify their claims and compare them against each-other?

So, what do you think about the “Greening of QoR?” Is it meaningful? If not, why not? And if yes, how can we go about it? It’s always fun to make predictions, so please do share yours …

About the Author – Chaitanya Rajguru

Chaitanya is an Associate Technical Fellow at KPIT Cummins Infosystems Ltd. He has extensive experience in end-to-end development of semiconductor products, from definition to production, with specialization in PC chipset, graphics and Flash memory IC products. He has played various roles such as product development lead, technical expert, people manager and organizational development facilitator.

On Monday, June 29th, we had our second event; a speech by Shrinath Keskar, former M.D. of Ikanos Communications in India. A good cross section of people attended the event and the discussion was quite lively. We had several new faces in the room, a definitive indicator of progress.  

We also have our first guest blog written by Chaitanya Rajguru of KPIT Cummins Infosystems, and this is really what we are looking for. I want more people to participate in group discussions and idea generation. Rather than having only just a handful of people writing content, involvement from all is needed if we want to keep growing and have a voice in the development of Pune as a Chip/Embedded design hub. 

Shrinath spoke about the challenges of designing chips for the telecom sector. The topic was quite relevant since we have several companies in the area that service Telecom applications. Shrinath not only focused on design challenges which generally revolve around the cost/power/features triangle, but also on challenges offered by the market; telecom standards, time to market and deployment. This was good information for engineers as it explained the logic behind many management decisions.  

Telecom standards, both wireline and wireless, drive how telecom companies go about their business. Standards not only have technical, but regulatory challenges associated with them. In addition, there are competing standards that try to solve the same problem (Fig 1) and technical slugfests go on for many years before a winner emerges.  

 

Many a times, the winning standard has such a short window of opportunity that it may be pointless to keep designing to it. Sometimes, governments propose standards in order to get access to advanced technology; China proposed WAPI a few years ago for wireless security. The catch was that anyone trying to sell Telecom equipment in China would have to disclose their technology to a Chinese partner if (emphasis is mine) WAPI had been adopted.

In order to support current and possibly future standards, chips have to be intelligently designed with possibly some redundant I/O, memory and cells which can be used to fix design faults or adapt to changing standards. Figure 2 below shows what a chip designer spends doing day in and out and to Shrinath’s point, there are lots of opportunities available for innovators to improve the design process – innovation does not need to end at the transistor level.

Where a Designer Spends All His Time, Source: Xilinx, 2004

Telecom equipment typically stays in the market for years as telecom standards take a while to roll out due to regulatory or geographical hurdles. However, a chip vendor hardly ever has that kind of time to supply the product. A telecom line card will be generally designed in 9-12 months and the chip must be designed, tested and deployed in the production line card within that timeframe. Time to Market is very important for Telecom OEMs; hence chip vendors must be able to convert design wins into production chips that work. 

Deployment is a very important phase in the life of a telecom chip. You can test the product in labs that mimic customer test environments, but you can never test for real situations such as interference from out of spec frequency bands. It is very important to have good support staff on hand to fight these battles alongside customers. Your chip must work in each and every deployment; even a 90% success rate will not cut it. 

As Moore’s law comes to the end of life, there is a lot of discussion happening around a new sustainable model for chip startups. The current model, which requires upwards of $50M in VC money to be profitable, cannot live for long. Very likely, the next invention in the semi/EDA market is going to be economic, something that allows new companies to form and prosper.

About the Author – Abhijit Athavale

Abhijit Athavale is the President and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at Taray, Inc and Sanved DA. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.

Well, I am quite excited to get the PuneChips forum up and running. While we would have liked to see more people attend, we had a good start. We invited most of the Semi/EDA folks in and around Pune and did get a very favorable response. Pending work and travel schedules are probably the culprits for a lower attendance, and I certainly hope that we will get more and more people to attend future events.

Ultimately, this forum is for the Semiconductor/EDA and Applications companies in and around Pune and we want to make sure that all future events/programs are catered to these companies needs. Again suggestions are most welcome and we are most certainly looking for individuals and companies to take on other responsibilities. We already have a taker for writing a guest blog so that is an encouraging sign.

That said, I want to thank Abhijit Abhyankar from Rambus for taking time out of his busy schedule to present to us. The presentation was packed with lots of information generated a healthy amount of discussion during and after. Abhijit mentioned falling productivity and increasing power consumption as the two most important industry challenges, and therein lie the opportunities. Due to progressively declining geometries, number of transistors per chip has exploded, creating all sorts of new challenges. Conventional problem solving approaches are not working and radically different methodologies are required.

Ever since Gordon Moore made his empirical observation that transistor densities will double every two years, the industry has been making concerted efforts to ensure that Moore’s law remains valid despite all predictions otherwise. Physical limits do certainly pose a challenge to increasing the transistor densities in two dimensions, but scientists are working on 3D placement of transistors, where transistors are either placed vertically, or on top of each other. Another approach to increase densities is to skip the third dimension altogether and go directly to the fourth, i.e. Time. Some programmable device makers think that you can make a cell or logic block on the chip perform different functions during a clock cycle resulting in extremely dense chips without pushing physical limits. If these efforts are successful, Moore’s law will continue to live for a long time.

Interestingly, Google’s founder Sergey Brin came up with a new term coined “Page’s Law” (watch this clip) named after his co-founder just last month. It states that software gets twice as slow every 18 months, explaining why your cell phones and PCs seem slower even as the HW inside remains unchanged. This new law seems to be destined as a sidekick of Moore’s law and may provide a reason for people to go buy new hardware every 18 months! Maybe, this is what they call a virtuous cycle …

Jokes aside, productivity and power are certainly a couple of areas that need solving in the near term.  SEMATECH or Semiconductor Manufacturing Technology Association has circulated this interesting chart which compares design complexities to designer productivity. This problem can certainly be solved by creating new tools that let the designer work from a much higher level than delving deep within the IC.

Design Complexity vs. Designer Productivity; Source: SEMATECH

Additionally, today’s chips consume too much power. Power analysis has become a huge time sink during chip design due to very high densities. It may not be an overestimation to claim that power related issues are a major cause of productivity losses during chip design. Newer techniques that allow designers to work on reducing power from the early design stages are required, in addition to new architectures that inherently consume less power.

I personally feel that Indian companies should rise up to solve this challenge. While we are not well set as far as semiconductor manufacturing goes, we are certainly on the ball with respect to VLSI design, verification, simulation, etc. We have the talent, the training and now, even the experience to tackle these challenges. To all the young entrepreneurs out there, look at the evolving opportunities in this sector; there certainly is a world beyond web 2.0.

Finally big thanks to Kaushik Gala and the NCL Venture Center for opening up their facilities to this group. Rarely do we see such well equipped meeting rooms and fabulous campuses. I also want to thank everyone who attended the inaugural event. We had some very senior people attend from QLogic, LSI, and KPIT Cummins. There are 12-13 more companies in the area and I would really like to encourage engineers working there to attend. There will be lots of opportunities to learn from industry experts, network and formulate your ideas. Keep in mind that we will not be able to distribute yesterday’s presentation to a wider audience so those that did not attend truly missed out. I expect this will happen in the future due to corporate guidelines, so it is important that people show up for the event.

Once again, thanks to everyone who helped get PuneChips off the Ground.

About the Author – Abhijit Athavale

Abhijit Athavale is the President and CEO of Markonix, and a high-tech marketing consultant. He has 16+ years of high-technology industry experience. Prior to Markonix, Abhijit spent over 11 years at Xilinx, Inc. in various engineering, applications and marketing roles. In his role as a marketing consultant, he has held executive management positions at Taray, Inc and Sanved DA. He has a masters degree in electrical engineering from Texas A&M University and a bachelors degree in electrical engineering from University of Pune. He is an accomplished speaker and author of several publications including a book.