ASIC « Pune's Semi/EDA & Embedded Forum

Free Event: Advanced System Verilog Tips Including OVM & UVM Tips by Cliff Cummings

By punechips

Cliff Cummings photograph

SystemVerilog Guru Cliff Cummings is back in town and he will be holding another seminar on April 19th at the MCCIA auditorium on Senapati Bapat Road from 4:00pm to 7:30pm. Most recently, Cliff was here in November 2009 and this seminar gives a great opportunity for engineers to re-engage with him. This event is completely free, but registration is required. Please visit this link to register and view the agenda.

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Chip Design Verification: Test-plan/Coverage Plan

By punechips

photo credit: oskay

This is the second in the blog series titled Field Manual for Verification Planning written for PuneChips by Suhas Belgal . The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.

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Cadence Acquires Taray

By punechips

FPGA as the PCB's Grand Central Station

Earlier this week, Cadence Design Systems acquired an EDA startup, Taray, Inc. Financial terms were not disclosed.

This is important because it is an Indian EDA product company story. While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.

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Introduction to Chip Verification Planning

By punechips

This is the first in a series of blogs written for PuneChips by Suhas Belgal titled Field Manual for Verification Planning. The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.

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SystemVerilog and Designer Productivity

By punechips

The most recent PuneChips event was easily the most successful one in the short history of the group. Over 50 engineers attended the “SystemVerilog” talk by Clifford Cummings (See Cliff’s Linked-in profile here), President of Sunburst Design and SystemVerilog industry guru. A big thank you to a few folks who made this possible is in order; first off Parag Mehta of Qlogic for connecting us with Cliff; secondly in addition to Parag, Pravin Desale and Deepak Lala of LSI, and Jagdish Doma of Virage Logic for driving the attendance. Last, but not the least, we must also thank Cliff for taking us through a complex topic in a very engaging manner. Cliff certainly held the audience in rapt attention through an hour of highly technical discussion. The Q&A session was also very engaging. Of course, Cliff being the industry celebrity that he is, was mobbed by engineers asking questions after his speech.

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New Techniques in ASIC Verification

By punechips

(This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. She is a PuneChips member.)

As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what.

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Free Event: Advanced System Verilog Tips Including OVM & UVM Tips by Cliff Cummings

Chip Design Verification: Test-plan/Coverage Plan

Cadence Acquires Taray

Introduction to Chip Verification Planning

SystemVerilog and Designer Productivity

New Techniques in ASIC Verification

PuneChips Calendar

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