FPGA as the PCB's Grand Central Station

Earlier this week, Cadence Design Systems acquired an EDA startup, Taray, Inc. Financial terms were not disclosed.

This is important because it is an Indian EDA product company story.  While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.

Nagesh Gupta, Taray’s CEO said, “This was an inspiring innovation done right from India. The technology, which includes two issued patents and one pending patent was developed entirely in Hyderabad.”

Nagesh Chillin' in California

Cadence is one of the big three EDA players in the world, or three and a half, if you count Magma. Cadence is very good at the ASIC design flow, however, their FPGA design flow is lacking. With the Synopsys acquisition of Synplicity last year, they were certainly playing catch-up. Taray’s product called 7Circuits fills a gap in their FPGA PCB co-design flow. Cadence had already signed an OEM deal with Taray last year and the question was not if, but really when the acquisition would happen. 7Circuits is an FPGA I/O Synthesis tool.  As all FPGAs are re-prgrammable, the IO assignments change every time you make a design revision. This is a significant problem if your PCB is already in production. As more and more FPGAs with thousands of pins are now hitting the market, an intelligent tool like 7Circuits is absolutely required to do this job. You can read all about 7Circuits here.

Why was Taray successful in making this happen? There are three major reasons. First, they identified a niche area where no current solution existed. Gupta has a very strong system design experience, and this was a problem that he personally had faced many times. Customers were using home made scripts and excel sheets to solve the problem. 7Circuits is not only easy to use, but delivers significantly better quality of results over current methods.  Secondly, Cadence was the perfect suitor. They had a weak FPGA product line, while the competition had better tools. Third, FPGAs are getting bigger and faster all the time, putting pressure on I/O. This trend will continue for a while as 40nm products have started shipping and 28nm is just around the corner. With advances in the lithography technologies, we may even see a dip below sub-micron geometries in the future. Looking at the growing FPGA market, Cadence can easily add $5m – $10m to their bottomline if they use the right pricing and selling strategies.

Indian EDA companies can indeed take heart from this, but they need to make sure that they are addressing the right market.  The mainstream EDA business is a mature business. As number of ASIC design starts continue to decline year over year, the market for super expensive, super complex design tools is dwindling; obviously there are fewer seats that can be sold every year. Plus, severe cost cuts at chip design houses mean lower budgets and lower margins for EDA tools. Focusing on the FPGA market makes a lot of sense as that is the only market that is growing in size. FPGA ASP has been rapidly falling in the last ten years meaning that the chips are much more affordable; something that was not true just a few years back. What this does is increase the number of designers working on FPGA based systems. By some counts, there are over 100,000 distinct FPGA customers not including smaller ones who buy from resellers. Compare this to tens or maybe just over a hundred chip designers and manufacturers. The only problem with FPGA houses is that they are used to free or cheap tools; they have been spoiled by the FPGA vendors who often offer free or really cheap software. That said, they always buy tools that have a compelling value to them.

The lesson learnt here is that rather than concentrating efforts on the ASIC design flow, look at the FPGA design flow and find niches that you can easily fill. The answer is going to be simpler and far easier to reach, especially from India. Secondly, do not try to price your products like the mainstream EDA vendors. If your tools incorporate a must-have feature set and are priced within reach of the average FPGA design house, they will sell. Remember, you are looking at hundreds of thousands of license in total, not a few hundred. After all, there is a fortune to made at the bottom of the pyramid. Lastly, work on your sales and marketing process. If you have tool chains that cost just a few hundred dollars, it is very likely that you can successfully use the internet to sell and market your tools and avoid the traditional rep – distributor model. As examples, signal integrity tools, DSP tools, embedded processing tools that just work only with the FPGAs are likely to be big markets as buying licenses from Mentor Graphics, or Mathworks, or Windriver is often out of reach of the average buyer.

This is the first in a series of blogs written for PuneChips by Suhas Belgal titled Field Manual for Verification Planning. The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.     

The objective of this series is to provide a view of the ‘art’ of design verification. Everyone has heard the quote “Verification is an NP complete problem – it can never be done”.  If so, how should one schedule the verification program? When is the chip really verification clear for tape-out or production? If it is art, how does one measure the quality? Or, how does one turn it into ‘science’ and bring predictability into the equation?  Recently, while reading Robert Pirsig’s famous book “Zen and the art of Motorcycle Maintenance”, the questions of ‘art’, ‘science’ and ‘quality’ of the chip being designed crossed my mind…This series will provide a practical insight into the various aspects of verification, different tools, methodologies, best known practices, key indicators, tracking and management while trying to reflect on the fundamental question of whether verification can be completed. All of these will help bringing in the much needed predictability into the verification program. However, all of the best know practices and automation tools in the world can still not replace the need for engineering intelligence. You still need the best and the brightest minds to tackle the challenges. On the flip side, this is what makes verification challenging and interesting, and will attract the best minds out there. So, sprinkled throughout this series, you will find the term ‘intellectual process’ or ‘intellectual exercise’; the part of the process which still needs human intelligence or an engineering discretion will be identified as the intellectual process or the intellectual exercise.The basic goal of any chip design verification project is to find ‘all’ the bugs before tape-out! One way to bring pragmatism is to clearly identify the context of the statement of bug free design. That is, the design should be bug free for a crisply identified goal such as ‘customer demo/samples’ or ‘to enable software development’.  Even with such constraints, it still remains to be an NP complete problem. This is where statistics, probability can come in, and various indicators can be used to define the verification quality.          

In addition to the fundamental goal, there are other objectives such as productivity, efficiency, resource usage, ‘finding critical bugs earlier’ and so on. These are as important, as a matter of fact, even more important oftentimes than the basic question of ‘have we caught all the bugs’.     

Basic Dimensions   

The three basic dimensions of verification are ‘Coverage’, ‘Stimulus’ and ‘Checker’. Regardless of the tools or methodology, any verification environment consists of these three parts.       

Coverage addresses the fundamental question of how complete the verification is. This being an NP complete problem can never be complete, theoretically. However, in reality, setting the ‘denominator’ of the ratio – ‘covered vs planned’, becomes an intellectual exercise. Certain practices and pitfalls will be covered in detail in the ‘coverage/testplan’ topic.      

Stimulus can be deterministic, but can explode very quickly. Say, a 2 input functional block can be covered exhaustively in 4 cases. But, a 256 input block will require  1.1579….e+77 combinations – impractical! Even worse, sequential elements add a time dimension. Finding proper methods to select or prioritize ‘important’ or ‘high leverage’ stimulus is an intellectual exercise.       

Checker or rather, not having a thorough checker will make the two other dimensions useless. One can have a ‘complete’ checker only if the definition of that the expected behavior is complete. Usually, this is covered by the Design or the Architecture Specification of the chip or the product. Proper interpretation and checking for completeness is an intellectual process.     

Flow/Process  

A typical flow involves the following steps/phases, interspersed with reviews (every phase should begin and end with reviews).       

1. Design/Specification study
2. Coverage planning (traditionally known as test-plan development)
3. Testbench design planning
4. Setting up the Verification Environment – databases, bug tracker, templates, regression/simulation environment, debug process, indicator tracking
5. Testbench implementation
6. Coverage plan implementation
7. Bringup (fresh RTL tested against fresh testbench)
8. Feature coverage
9. Coverage exploration
10. Final Checklist

Verification Methods  

Several methods can be employed to carry out pre-silicon verification. The primary being Simulation based, Emulation based and the Formal method. All have pros and cons and can be used to complement each other.       

Simulation method utilizes dynamic simulation techniques used at different scopes such as ‘module or block’ level, ‘cluster’ level or the ‘full chip’ level.  Lower granularity helps speed up simulations, catch basic bugs quickly.  However, cluster or full chip environments help check the interactions between the blocks, which are a common source of bugs. However, at higher levels, simulation speed slows down, and one starts encountering ‘controllability/observability ’ problems.       

Emulation, hardware acceleration, proto-typing allows testing at much higher speed, and possibly at-speed.  Hardware/software co-verification, using real life devices can be accomplished using emulators.  Primary advantage is to get large number of cycles needed reach certain states of the design, say testing thousands of HD video frames. Also, one can actually bring-up peripheral devices such as SATA hard drives, thus taking out any risk in the implementation. Downsides are the cost and debug ability.       

Formal methods prove behavior of a certain section of the design to match a certain set of properties mathematically. Thus, it’s exhaustive and complete! However, there are logistical limitations to the current generation of tools such as design size, speed, and even then, coverage is still only as good as the property set. Defining the property set is an intellectual process.     

Productivity  

Productivity or the efficiency pertains to the processes, environment, tools, methods which can improve the verification cycle. The major costs are the ‘direct’ $ cost, human power cost and the cost in terms of total calendar time.  Simulators, emulators, server farms, other tools contribute to the direct $ cost. Calendar time is the critical path, and accounts for the processes that cannot be temporally scaled.       

Buy vs. brew is always an important decision, and comes across multiple times during a project. The maintenance cost of developing a tool in-house should not be ignored while making this decision.       

The non-deterministic, open-ended nature of verification complicates resource planning too. Predicting the number of simulation licenses needed, server farm size/capacity and estimating the total cycles needed to flush out ‘all the bugs’ is an intellectual process.       

Simulation license usage, cycles, build times, run-times need to be tracked before they can be improved. Scripts/tools to track these indicators should be planned for. In addition, the bug tracking (rate of opening/closing bugs, turnaround times etc), rate of test development, coverage improvement needs to be constantly measured for improvement.     

Environment   

Verification Environment is a key part of the verification project. This includes organizing the verification collateral, selecting an efficient and robust revision control system, work flow, automation to avoid manual mistakes and improve efficiency, integration of various pieces of verification and choosing an efficient platform for the entire team, including designers, to develop complex projects. And, in today’s global development community, an efficient environment is the key to success. Groups can be spread all over the world, but their development environment should be identical or seamless.       

Discipline and attention to detail are extremely important. How many times have we heard or experienced cases where bugs have slipped through the cracks in spite of having a ‘test’ that should have caught them – just because the test was not run on the final version of the netlist, or the test was not a part of a certain regression list. These mistakes are expensive, to say the least. Adding mere stress and pressure on engineers doesn’t help either. A fool-proof process and a set of tools/scripts can mitigate these circumstances.     

Verification Language    

The biggest wars in the verification world are on this topic. The modeling language for creating test-bench and the tests is central to any verification strategy. Starting with a bit of a historical perspective, Verilog or VHDL have been traditionally used for verification along with design. The ‘behavioral’ constructs in these languages aid verification tasks. Even today, several companies/projects rely on verification strategies based entirely on Verilog or VHDL. Using Verilog or VHDL has its advantages; the language knowledge is universal, no special simulators are needed, and most of the EDA tools understand and support these languages. On the downside, these languages were primarily designed to describe digital circuits/logic. They don’t have powerful data structure constructs. Randomization support is very limited.       

To circumvent these limitations, common powerful languages/scripts such as C and Perl have been introduced. C or Perl provide the language or programming power. However, they are still not specifically ‘verification languages’, and every project/company tend to have their own implementation of the methodology.       

Over 10 years ago, a new breed of specialized languages known as ‘Hardware Verification Languages (HVL)’ came into existence, starting with Vera and Specman. Vera was born inside Sun Microsystems as an internal verification language/tool. This was spun off and eventually became part of Synopsys. Most recently, the industry trend has been towards SystemVerilog, in an effort to standardize on the language.  HVLs provide strong Object Oriented Structure and advanced features for randomization and constraint solving. In addition, they have become platforms for myriad of verification functions such as coverage monitoring, assertions and so on.      

Finally, the most recent development has been that of a methodology layer via libraries. VMM, OVM are the two main methodologies in the market today for System Verilog.      

One could argue that everything that is provided by these higher level HVLs or the libraries can be implemented in Verilog or VHDL. True! But, firstly you get a tremendous boost in productivity as these libraries or languages provide a high number of pre-defined functions, constructs. Secondly, these libraries provide a framework that inherently makes the collateral reusable and efficient.        

Random, Directed, Emulation?     

Another contentious area for design and verification teams is to decide between random, constrained random or directed testing. Another dimension of this debate is the simulation vs. emulation decision. The pros and cons will be discussed in detail in a future article of this series.        

Sometimes, it helps using analogues. For instance, how would one test out a car – would one use a test-track with ‘simulated’ skids, obstacles and other external environmental factors, or just drive 100K miles on an expressway. One could use this analogy further and even look at orthogonals – say, if the blinkers have been tested in the garage, is it necessary to test them while driving through winding hilly roads, or say, while driving through winding hilly roads while the outside temperature is sub zero and at night. This helps reduce the set of interesting test cases.      

Reviews/Checklist    

As mentioned earlier, discipline is very important in Verification. Verification is the final safety net prior to tape-out. Any hole can potentially cost millions. In addition to inserting checks and balances into the tools/scripts/processes, reviews and checklists have a significant role in any verification project.        

For reviews, key things to understand are:      

• Primary intent should be to solicit feedback from other team members. Thus, every attempt should be made to communicate the content clearly to the attendees. A good idea or a clarification or detection of an error can save lots of time, frustration downstream.
• Put as many figures, tables as possible. Avoid textual paragraphs. A picture is worth 1000 words!
• Example code review is highly recommended.
• Time should be used efficiently but one should not limit wall-clock times     

Some of the useful review/checklists, other than the usual, are:      

• Tape-out checklist. Some of the items are
  • Waived coverage points or tests along with justification
  • Waived bugs along with justification
  • Uncovered planned items, if any, with justification/risk assessment
  • ‘What-else’ checklist: Once all the planned verification activities are completed along with a satisfactory bug curve, a series of what else reviews are recommended. This is a free flowing brainstorming of what else can possibly be done to find the bugs. As we all know, all bugs can never be found – which also means there are always more bugs in the design to be found and these reviews can potentially lead to them.
  • ‘Last set of bugs’ – (This category or the review needs a better name!): Towards the end, around the time the ‘what-else’ reviews are held, the last set of bugs uncovered should be reviewed or analyzed for the following:
    • What found the problem – was it accidental?
    • What caused the bug – did it exist all along or a recent event caused it?
    • Could it have been caught earlier?
    • What if it had slipped? Is there a workaround? This tells the severity of the bug    

These questions and discussions usually give rise to a few more clues or ideas about how to look for the remaining residual bugs.      

Modeling     

Modeling is a very generic term. In the context of verification, this is used for a ‘model’ that describes the correct or golden behavior. Often times, this arises out of architectural exploration efforts.        

Models can be developed in C (most common), MatLab, SystemC, SystemVerilog, and Verilog or for that matter, any language.        

When used as a golden model for verification purposes, it is very important to consider the verification requirements as this can have a very high impact on the productivity or efficiency of the project.  Most of the time, there are surprises, as the models are developed much before verification starts and/or by different groups. Avoid them by planning and collaborating ahead of time with the modeling team. Verifying these models independently is always an interesting and important problem.     

Performance Verification     

This being very important, requires explicit attention. Performance, as opposed to functional verification, can be tricky due to two things. Firstly, setting up cases or ‘checking mechanism’ is not covered by the traditional functional verification collateral – thus, it is more work and often comes as a surprise. Secondly, identifying, defining and quantifying performance metrics is non-trivial. For instance, if the specification identifies the startup time of, say, a product like an iPod to be less than 2 seconds, then one needs to identify functionality in the hardware that contributes to this delay and then use that number to check for correctness. Sometimes, ‘quality’ aspects are not clearly quantified – especially, the acceptable numbers. Video quality is a good example of this.      

Other Verification Areas     

While planning for verification, following areas or special cases need to be considered   

• Handling clock domain crossings
• Simulation artifacts, for instance, code that could mask propagation of Xs
• Design rule violations that will not be caught during traditional simulation/emulation
• Check for  potential errors introduced by the RTL -> GDS process
• Analog components, and their interface with the digital logic
• Process variations and the logic implemented to compensate, for instance, DLLs.
• Power simulations are going to be commonplace going forward

Example DUT     

Let’s take an example DUT – a simple SOC. We will throw in some standard SOC components – a host processor, a co-processor (such as a DSP or some such computational element), internal buses for both control and high speed data transfers, a memory sub-system (DDRs, SRAMs), peripheral IO interfaces such as USB, PCIe, UART, and internal SOC control elements such as IO muxes, clock/power management unit, interrupt management unit.       

The following block diagram illustrates our example. All the future topics in this series will be discussed in the context of this example. 

Example of a SoC DUT

Summary

Throughout this series, we will make an effort to identify the ‘art’ and ‘science’ involved in Chip verification, with practical tips or some of the best known practices. Through use of advanced techniques, tools, methods, discipline, best practices one can mitigate the non-deterministic nature of verification. These can be used for accurate scheduling, planning and a high quality execution of verification projects leading to successful first pass silicon. However, there is an ‘intellectual’ part of the process that still requires the best and the brightest minds.  And, that’s where the satisfaction or the intellectual rewards lie. Verification accounts for 70% of the pre-silicon development efforts, according to some estimates – let’s not leave it to chance by quoting the famous ‘verification is an NP complete problem’ – it can be harnessed and this has been already demonstrated by several successful groups, companies.       

In the next session, we will cover ‘test-plan/coverage plan’ topic in detail.       

About the Author:  Suhas Belgal has 17 plus years of experience in Chip Design, Emulation, Modeling and Verification, including 9 years as a Verification Manager. During these years, Suhas has worked for several multi-billion dollar companies such as Intel and LSI, various start ups, and co-founded a Verification Services company. Over the years, Suhas has played key roles several high profile design teams such as Pentium II, and successfully led several SoC chips to production.  He has experience in a wide range of Verification Methods and tools, and has been a presenter and panel member at various conferences, including the DAC. He has a master’s degree in EE from University of Texas at Austin and a bachelor’s from VJTI, Mumbai.      

This content has been licensed to PuneChips under a Creative Commons Attribution-Noncommercial 2.5 India License. Contact Suhas Belgal for details of how to attribute and re-use for non-commercial as well as commercial distribution.    

It is very clear that SystemVerilog is clearly targeted at improving designer productivity. Failing productivity due to increasing design complexity is one of the biggest challenges faced by chip designers today, and it is not at all surprising that the EDA tool industry is focused on rectifying this. The chart below (source: SEMATECH) shows a rather grim picture – while design complexity has been growing at 58% CAGR, productivity has been increasing at only 21% CAGR. It is obvious to anyone that tools that fill this gap will be in great demand.

The reason for increasing design complexity is multifold – decreasing geometries allow designers to add more and more elements to the chip, making the entire process challenging. Number of IP cores per chip has grown from ~30 in 2003 to over 250 in 2006 and possibly much more today (source: EETimes). In addition, a big bull’s eye has been painted on power consumption numbers and most chips now must be designed using low power techniques. Plus, increasing complexity means that chip verification becomes more complex; 50% of all ASIC designs today require respins due to functional/logic errors (Source: Colette International Research).

Rather than a single solution, it is very likely that a multitude of innovative solutions that address individual problems will emerge. For example, better modeling techniques that can give a very accurate QoR estimate at the architecture stage itself can reduce the design complexity downstream. Languages such as SystemVerilog literally reduce the lines of code that a designer or verification engineer must write, thus boosting productivity. Time also may be right for ESL design, which has been around for a while, as conventional techniques fail to keep up. 

All in all, we live in very interesting times. Faster and smaller is not always for the better. The industry must innovate and rise up to the economic and design challenges if it is to survive and prosper.

As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what.

ESL or Electronic System Level testing is the newest trend. Supporters of ESL claim that it is a highly powerful system level modeling tool. It enables fast software bring-up if combined with an emulation/FPGA prototyping platform. ESL has been used successfully to validate systems for mobile applications where only one peripheral/application is active on the processor bus. ESL does not seem suitable for systems where multiple processes and interfaces are active simultaneously, like for example in a networking system.

Formal verification, a static verification technique which is mainly assertion based, is useful to check control paths. It cannot be used to verify datapaths. Dynamic simulation is a very effective way of verifying functionality of every block in the ASIC including the datapath. Gate level simulations performed after the back annotated placement and routing data is available are used to identify timing related issues or omissions/errors in stating multi-cycle paths.

The need to find hardware bugs as early as possible in the ASIC lifecycle drives the emulation and/or FPGA prototyping effort. Both these techniques enable the testing of scenarios which are generally not possible to test in dynamic functional verification, well before the actual silicon comes back from the fab. Emulation or prototyping also accelerate fast software ramp up and the software team can get a development platform ready well before the actual chip is available. Emulation involves running test cases on hardware accelerated platforms like Palladium from Cadence and Veloce from Mentor. For FPGA prototyping, Single or multiple FPGAs are used to build a PCB system targeted for the testing of the ASIC/SoC. The ASIC code is then fully or partially programmed on the FPGA/s and functionality can thus be tested.

Scenarios with much longer simulation times than what normal functional simulation allows can be run on the emulation platforms. All the internal signals are available for viewing and debug, just like in functional simulation. The FPGA prototype platform does enable longer test time, but the debugging available is limited. The hardware accelerators are costly, and investing in them makes sense if a company has lot of ASIC programs running simultaneously. For companies which have similar chips planned back to back, investing in a home grown FPGA based emulation/prototyping platform makes sense. Another advantage FPGA prototyping is that the RTL goes through a complete synthesis and place and route cycle and testing is done on a circuit which is as close to the real ASIC as possible.

To ensure that a bug free product reaches the customer is a complex activity and poses multiple challenges. Coverage, legacy code, repeatability are issues that need to be tackled. Ensuring that the coverage is at an acceptable level is important. Code coverage is run to find out if all the possibilities of a written code are exercised in a test suite. Simulators from cadence (ius), synopsys(vcs) and mentor (modelsim) have their own code coverage analyzers. Functional coverage means to find out if each feature listed in the specification for an ASIC/SoC is verified. It is essential that the functional specification document has an individual numbered paragraph for each feature so that traceability is easier. Functional coverage is an activity that needs planning, reviews and careful test case designing. Methodologies like eRM (e reuse methodology – Specman based) and OVM (open verification methodology – System verilog based) do assist checking functional coverage, but the inputs provided need careful specification and reviews.

Reviews, not just for coverage, but at every stage in the ASIC cycle are extremely important. One of the challenges encountered while designing an ASIC is that the hardware team interprets a certain behavior from software and the software expects that certain things are taken care of in hardware. It is very important to involve members from design team, verification team, architecture team, software & firmware team for verification review.

It takes a good amount of effort to come up with a verification environment, and it is very common for a team to use what has worked before when schedules are demanding. Legacy environment saves lot of time, but it also handicaps the team. Talking about saving time, efficiency goes a long way in shrinking the schedules. The initial time and effort investment in automation of repetitive tasks save lot of time in future. Use of re-usable methodologies will definitely save time and effort.

Finally, while choosing the verification flow for a certain ASIC, team needs to look at what is available in terms of resources as well as time, understand the end user requirement, and make a decision on which technique to employ at what stage.

About the Author

Arati has close to 9 years experience in ASIC front end design and verification. Post silicon validation and FPGA prototyping is her recent area of interest and expertise. Arati has worked with Wipro Technologies and Conexant Systems. Arati did her B.E. from University of Pune and M.Tech from CEDT, Indian Institute of Science, Bangalore. See her linked-in profile for more details.

So where does one begin? One good starting point may be with a popular indicator used to gauge the “goodness” of EDA tool’s output: “Quality of Results”, or QoR. QoR is used as a higher-level indicator of process quality, much like a Customer Satisfaction Index that up-levels feedback on specific aspects such as timely delivery and responsiveness. IC design EDA tools have used to showcase what they can do. So is it possible to expand its scope to include “greenness” as well? Or is it just an attempt to paint a turkey blue and pass it off as a peacock?

QoR is one of the long-lived and often-used keywords in Silicon Valley – surely on par with “information superhighway” in sheer citation count. Yet the latter phrase isn’t heard much anymore. It just reminds us of the 90’s internet boom, and doesn’t convey anything that is new today. After all, this superhighway is now as much part of our lives as electric power distribution is, and it has been a while since either created much excitement. And so is “QoR” similarly frozen in time as well, not staying up-to-date with today’s design challenges?

Let us take a quick look at how QoR has evolved over time. In the early days of IC design, the biggest challenge was to pack as many transistors onto a single die as possible. The self-fulfilling prophecy of Moore’s Law had setup expectations that somehow had to be met! And while the accompanying frequency spiral required lots of efforts to maintain, it was achievable. Thus the QoR directly reflected “transistor count” and “frequency” as the most important indicators of EDA tool capability. Other variations appeared, such as the packing density of logic and analog circuitry.

“Power” then appeared on the QoR scene, as limits of battery power and even socket power were approached by systems. Now EDA vendors could speak the language of the system architects with their “power-performance-area” optimization triangle. Higher-level performance metrics such as MIPS and FLOPS entered. Then came combinations such as “MIPS per megahertz per watt.” Thus the QoR definition expanded from the “micro” qualities to encompass the “macro”: from frequency and packing density to power and performance.

Looking at current trends in the economy, “Going Green” has taken on big importance everywhere. It is the socio-politically correct thing to do, regardless of your product or service. Companies with physical products joined the bandwagon early: building architects, automobile manufacturers, consumer electronics OEMs, and IC manufacturers. One software company that has made a start is Google, with its goal to “minimize its carbon footprint.” Other companies have been slower to adapt – maybe due to having “soft products,” or maybe because they find it hard to make the right connection into this trend. But the semiconductor industry and the EDA industry are inevitably subject to the same greening trend, and can not convincingly “opt out.”

But “Being Green” is as high-level a quality metric for an EDA product as any – so much so, that whether it even applies to EDA tools is sure to be hotly debated. Yet suppose, for a moment, that it were to be made a part of QoR, how do you think it can be done?

Initial thoughts that come to my mind suggest getting a “Green Process” certification for the EDA tool development cycle, analogous to the ISO9001 or CMMI certifications. In the future, such certifications could surely be applicable to any business or organization (maybe even an individual!), and the EDA industry would be no exception. Another possibility is to publish a “carbon footprint” or “carbon neutrality indicator.”

But the above “green indicators” apply only to the development of the EDA tools, and give no satisfactory indication of whether their use will lead to “green products”. My best suggestion so far to gauge that quality is to measure the tool performance (the fewer compute cycles it burns, the better) and its reuse (the more, the better). Reuse can be in terms of reusing the building blocks (within a project), the output (across projects) and even the hardware utilization (e.g. exploiting multicore architectures). I believe these quality measures will anyway be applied to the evaluation of EDA tools, because they also affect development cost and schedule. So one might as well explicitly go after these indicators and kill two birds in one stone!

On the downside of a green QoR, we could be chasing a red herring. Isn’t it be better to focus on the core job of the EDA tool, which is to make the design task easier? To what extent do we go in order to conform to this latest fad? And how about degrees of greenness, and who measures those? If two tool vendors claim to be green, how do I verify their claims and compare them against each-other?

So, what do you think about the “Greening of QoR?” Is it meaningful? If not, why not? And if yes, how can we go about it? It’s always fun to make predictions, so please do share yours …

About the Author – Chaitanya Rajguru

Chaitanya is an Associate Technical Fellow at KPIT Cummins Infosystems Ltd. He has extensive experience in end-to-end development of semiconductor products, from definition to production, with specialization in PC chipset, graphics and Flash memory IC products. He has played various roles such as product development lead, technical expert, people manager and organizational development facilitator.