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	<title>Pune&#039;s Semi/EDA &#38; Embedded Forum &#187; FPGA</title>
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	<description>Pune&#039;s Forum for Semiconductor/EDA and Embedded Design</description>
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		<title>Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</title>
		<link>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/</link>
		<comments>http://punechips.com/pci-express-architecture-and-applications-for-fpgas/#comments</comments>
		<pubDate>Thu, 21 Jul 2011 10:48:56 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[featured]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Serial IO]]></category>
		<category><![CDATA[PCI Express]]></category>
		<category><![CDATA[serial IO]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=273</guid>
		<description><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/" [...]<br />
<p>Continue reading <a href="http://punechips.com/pci-express-architecture-and-applications-for-fpgas/">Free Event: PCI Express Architecture and Applications for FPGAs by Kiran Puranik</a></p>]]></description>
			<content:encoded><![CDATA[<p><a href="http://http://www.pcisig.com/specifications/pciexpress/"><img class="alignnone size-full wp-image-274" title="PCI Express" src="http://punechips.com/wp-content/uploads/2011/07/PCIe.gif" alt="PCI Express" width="147" height="55" /></a></p>
<p>This is a <a href="http://punechips.com/">PuneChips </a>event, a forum for Pune people interested in semiconductors design/apps/EDA</p>
<p>What: A Talk on PCI Express Architecture and Applications for FPGAs by Kiran Puranik<br />
When: July 30, 2011 from 10:30 am to 12:00 noon<br />
Where: <a href="http://www.sadakmap.com/p/Venture-Center-NCL-Innovation-Park-2/">Venture Center</a>, NCL Innovation Park, Pashan Road</p>
<p><a title="PCI Special Interest Group website" href="http://www.pcisig.com/specifications/pciexpress/" target="_blank">PCI Express</a> Architecture and Applications for FPGAs</p>
<p>Modern FPGA devices offer great advantages for designers of industrial imaging, networking, automation and control, data acquisition systems for test, industrial and medical applications. Apart from offering high performance programmable fabric, FPGAs offer a wide variety of IO standards  to interface with networks, motors, sensors, transducers, offer built in high density data storage and the ability to interface to high speed external memory devices. But, most importantly FPGAs offer Gigabit serial connectivity via standards based protocols such as PCI Express<sup>TM</sup>. The ubiquitous nature of PCI Express technology enables development of FPGA based plug and play board and card products that interface with standard off-the-shelf embedded compute and communications platforms, running Windows<sup>TM</sup>, Linux or other operating systems and custom device drivers. PCI Express 3.0 Architecture offers many reliability, availability and scalability features to address application needs, as well as advanced features such as relaxed transaction ordering, transaction processing hints, optimized buffer flush-fill, active power management to achieve the highest throughput performance possible within the platform’s power and thermal budgets.</p>
<p><strong>About the speaker: <a title="Kiran Puranik Profile" href="http://www.linkedin.com/pub/kiran-puranik/4/945/647" target="_blank">Kiran Puranik</a></strong></p>
<p><strong></strong>Kiran is a Principal Architect at Xilinx, Inc., responsible for serial connectivity protocol products such as PCI Express. He has spent the last 10 years at Xilinx engaged in architecture definition, design, development and verification of Intellectual Property blocks for several generations of FPGAs. Before Xilinx, Kiran held various engineering positions in the field of ASIC, ASSP design and ICCAD software development.</p>
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		<title>FPGA Virtual Summit is here again</title>
		<link>http://punechips.com/fpga-virtual-summit-is-here-again/</link>
		<comments>http://punechips.com/fpga-virtual-summit-is-here-again/#comments</comments>
		<pubDate>Wed, 01 Jun 2011 05:52:47 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[Digital Design]]></category>
		<category><![CDATA[event]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[Military]]></category>
		<category><![CDATA[semiconductor]]></category>
		<category><![CDATA[Telecom]]></category>
		<category><![CDATA[Video]]></category>
		<category><![CDATA[communications]]></category>
		<category><![CDATA[military]]></category>
		<category><![CDATA[video]]></category>
		<category><![CDATA[virtual conference]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=248</guid>
		<description><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&#38;eventid=309275&#38;sessionid=1&#38;key=A0209A9A7EF30D447CC09931B20BF03E&#38;partnerref=osmpromo1&#38;sourcepage=register " target="_blank">here </a>for registration.</p>
<p><a href="http://punechips.com/fpga-virtual-summit-is-here-again/" [...]<br />
<p>Continue reading <a href="http://punechips.com/fpga-virtual-summit-is-here-again/">FPGA Virtual Summit is here again</a></p>]]></description>
			<content:encoded><![CDATA[<p>This year&#8217;s virtual summit will be held on June 23, 2011. I like virtual summits as they allow participants from all over the globe participate in discussions rather than limit them to a few local attendees. Granted, the timing is odd for India but people are known to work late nights to satisfy their bosses in the Valley. So, attending this is not too far fetched. For those interested, please <a title="FPGA Summit" href="http://www.fpgasummit.com/" target="_blank">visit </a>for information. Click <a title="FPGA Summit Registration" href=" https://event.on24.com/eventRegistration/EventLobbyServlet?target=registration.jsp&amp;eventid=309275&amp;sessionid=1&amp;key=A0209A9A7EF30D447CC09931B20BF03E&amp;partnerref=osmpromo1&amp;sourcepage=register " target="_blank">here </a>for registration.</p>
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		<title>Cadence Acquires Taray</title>
		<link>http://punechips.com/cadence-acquires-taray/</link>
		<comments>http://punechips.com/cadence-acquires-taray/#comments</comments>
		<pubDate>Thu, 25 Mar 2010 09:50:24 +0000</pubDate>
		<dc:creator>punechips</dc:creator>
				<category><![CDATA[ASIC]]></category>
		<category><![CDATA[EDA]]></category>
		<category><![CDATA[featured]]></category>
		<category><![CDATA[FPGA]]></category>
		<category><![CDATA[technology]]></category>
		<category><![CDATA[news]]></category>

		<guid isPermaLink="false">http://punechips.com/?p=122</guid>
		<description><![CDATA[<div id="attachment_126" class="wp-caption alignnone" style="width: 310px"><a href="http://punechips.com/wp-content/uploads/2010/03/PCB1.png"><img class="size-medium wp-image-126 " title="FPGA I/O Connections" src="http://punechips.com/wp-content/uploads/2010/03/PCB1-300x195.png" alt="FPGA I/O Connections" width="300" height="195" /></a><p class="wp-caption-text">FPGA as the PCB&#39;s Grand Central Station</p></div>
<p>Earlier this week, Cadence Design Systems acquired an EDA startup, <a href="http://www.tarayinc.com">Taray, Inc</a>. Financial terms were not disclosed.</p>
<p>This is important because it is an Indian EDA product company story.  While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.</p>
<p><a href="http://punechips.com/cadence-acquires-taray/" [...]<br />
<p>Continue reading <a href="http://punechips.com/cadence-acquires-taray/">Cadence Acquires Taray</a></p>]]></description>
			<content:encoded><![CDATA[<div id="attachment_126" class="wp-caption alignnone" style="width: 310px"><a href="http://punechips.com/wp-content/uploads/2010/03/PCB1.png"><img class="size-medium wp-image-126 " title="FPGA I/O Connections" src="http://punechips.com/wp-content/uploads/2010/03/PCB1-300x195.png" alt="FPGA I/O Connections" width="300" height="195" /></a><p class="wp-caption-text">FPGA as the PCB&#39;s Grand Central Station</p></div>
<p>Earlier this week, Cadence Design Systems acquired an EDA startup, <a href="http://www.tarayinc.com">Taray, Inc</a>. Financial terms were not disclosed.</p>
<p>This is important because it is an Indian EDA product company story.  While Taray, Inc. is a California corporation, the entire 7Circuits business plan, strategy, product definition and development was conceived in Hyderabad; even their CEO was in Hyderabad till he decided to move to the Silicon Valley to push the sales and marketing process. On top of it, this was a bootstrapped operation with no venture money involved. While Western companies have purchased Indian product companies in the past, majority of the deals haven been in the IT services, BPO, KPO or web 2.0 fields. An Indian EDA product company getting acquired has to be a watershed event.</p>
<p>Nagesh Gupta, Taray&#8217;s CEO said, &#8220;This was an inspiring innovation done right from India. The technology, which includes two issued patents and one pending patent was developed entirely in Hyderabad.&#8221;</p>
<div id="attachment_132" class="wp-caption alignnone" style="width: 310px"><a href="http://punechips.com/wp-content/uploads/2010/03/Nagesh-Photo.jpg"><img class="size-medium wp-image-132" title="Nagesh Gupta" src="http://punechips.com/wp-content/uploads/2010/03/Nagesh-Photo-300x225.jpg" alt="Nagesh Gupta" width="300" height="225" /></a><p class="wp-caption-text">Nagesh Chillin&#39; in California</p></div>
<p>Cadence is one of the big three EDA players in the world, or three and a half, if you count Magma. Cadence is very good at the ASIC design flow, however, their FPGA design flow is lacking. With the Synopsys acquisition of Synplicity last year, they were certainly playing catch-up. Taray&#8217;s product called 7Circuits fills a gap in their FPGA PCB co-design flow. Cadence had already signed an <a href="http://www.soccentral.com/results.asp?CatID=589&amp;EntryID=28742">OEM deal</a> with Taray last year and the question was not if, but really when the acquisition would happen. 7Circuits is an FPGA I/O Synthesis tool.  As all FPGAs are re-prgrammable, the IO assignments change every time you make a design revision. This is a significant problem if your PCB is already in production. As more and more FPGAs with thousands of pins are now hitting the market, an intelligent tool like 7Circuits is absolutely required to do this job. You can read all about 7Circuits <a href="http://www.tarayinc.com/overview.php">here</a>.</p>
<p>Why was Taray successful in making this happen? There are three major reasons. First, they identified a niche area where no current solution existed. Gupta has a very strong system design experience, and this was a problem that he personally had faced many times. Customers were using home made scripts and excel sheets to solve the problem. 7Circuits is not only easy to use, but delivers significantly better quality of results over current methods.  Secondly, Cadence was the perfect suitor. They had a weak FPGA product line, while the competition had better tools. Third, FPGAs are getting bigger and faster all the time, putting pressure on I/O. This trend will continue for a while as 40nm products have started shipping and 28nm is just around the corner. With advances in the lithography technologies, we may even see a dip below sub-micron geometries in the future. Looking at the growing FPGA market, Cadence can easily add $5m &#8211; $10m to their bottomline if they use the right pricing and selling strategies.</p>
<p>Indian EDA companies can indeed take heart from this, but they need to make sure that they are addressing the right market.  The mainstream EDA business is a mature business. As number of ASIC design starts continue to decline year over year, the market for super expensive, super complex design tools is dwindling; obviously there are fewer seats that can be sold every year. Plus, severe cost cuts at chip design houses mean lower budgets and lower margins for EDA tools. Focusing on the FPGA market makes a lot of sense as that is the only market that is growing in size. FPGA ASP has been rapidly falling in the last ten years meaning that the chips are much more affordable; something that was not true just a few years back. What this does is increase the number of designers working on FPGA based systems. By some counts, there are over 100,000 distinct FPGA customers not including smaller ones who buy from resellers. Compare this to tens or maybe just over a hundred chip designers and manufacturers. The only problem with FPGA houses is that they are used to free or cheap tools; they have been spoiled by the FPGA vendors who often offer free or really cheap software. That said, they always buy tools that have a compelling value to them.</p>
<p>The lesson learnt here is that rather than concentrating efforts on the ASIC design flow, look at the FPGA design flow and find niches that you can easily fill. The answer is going to be simpler and far easier to reach, especially from India. Secondly, do not try to price your products like the mainstream EDA vendors. If your tools incorporate a must-have feature set and are priced within reach of the average FPGA design house, they will sell. Remember, you are looking at hundreds of thousands of license in total, not a few hundred. After all, there is a fortune to made at the bottom of the pyramid. Lastly, work on your sales and marketing process. If you have tool chains that cost just a few hundred dollars, it is very likely that you can successfully use the internet to sell and market your tools and avoid the traditional rep &#8211; distributor model. As examples, signal integrity tools, DSP tools, embedded processing tools that just work only with the FPGAs are likely to be big markets as buying licenses from Mentor Graphics, or Mathworks, or Windriver is often out of reach of the average buyer.</p>
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