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Dr. Ramachandran also presented this at the 2011 VLSI conference. They have posted it online. Click here to download the PDF.This event is jointly brought to you by PuneChips and LSI Corporation.
Continue reading Presentation Now Available: Building an Autonomous and Scalable Semiconductor VLSI Business On November 11, 2010, Pune Mirror did a story on investments related to Storage, Networking and Computing chips in Pune. The story is not available online unfortunately, but can be read in the e-Paper version, under ‘City’ section, Page 07. For those who are interested in reading this article, we are uploading a scanned copy of this story. Read it here: Pune Area Hi-Tech Investments Total [...] Continue reading Pune Area Hi-Tech Investments At $1B
This a joint event organized by PuneChips and IIT Bombay Alumni Association – Pune Chapter. PuneChips a forum for Pune people interested in semiconductors design/apps/EDA. For details see http://www.punechips.com The most recent PuneChips event was easily the most successful one in the short history of the group. Over 50 engineers attended the “SystemVerilog” talk by Clifford Cummings (See Cliff’s Linked-in profile here), President of Sunburst Design and SystemVerilog industry guru. A big thank you to a few folks who made this possible is in order; first off Parag Mehta of Qlogic for connecting us with Cliff; secondly in addition to Parag, Pravin Desale and Deepak Lala of LSI, and Jagdish Doma of Virage Logic for driving the attendance. Last, but not the least, we must also thank Cliff for taking us through a complex topic in a very engaging manner. Cliff certainly held the audience in rapt attention through an hour of highly technical discussion. The Q&A session was also very engaging. Of course, Cliff being the industry celebrity that he is, was mobbed by engineers asking questions after his speech. (This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. She is a PuneChips member.) As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what. First, an update on PuneChips – we now have PuneChips Inaugural Event Well, I am quite excited to get the PuneChips forum up and running. While we would have liked to see more people attend, we had a good start. We invited most of the Semi/EDA folks in and around Pune and did get a very favorable response. Pending work and travel schedules are probably the culprits for a lower attendance, and I certainly hope that we will get more and more people to attend future events.
Continue reading Semiconductor Industry: Trends and Challenges |
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