Sandeep Sane has shared his presentation with PuneChips. Please download here: Electronics [...]
Continue reading Electronics Packaging Presentation now available
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This is the second in the blog series titled Field Manual for Verification Planning written for PuneChips by Suhas Belgal . The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase.
Continue reading Chip Design Verification: Test-plan/Coverage Plan
This is the first in a series of blogs written for PuneChips by Suhas Belgal titled Field Manual for Verification Planning. The blogs deal with functional verification of digital ICs and cover mostly the pre-silicon verification phase. The most recent PuneChips event was easily the most successful one in the short history of the group. Over 50 engineers attended the “SystemVerilog” talk by Clifford Cummings (See Cliff’s Linked-in profile here), President of Sunburst Design and SystemVerilog industry guru. A big thank you to a few folks who made this possible is in order; first off Parag Mehta of Qlogic for connecting us with Cliff; secondly in addition to Parag, Pravin Desale and Deepak Lala of LSI, and Jagdish Doma of Virage Logic for driving the attendance. Last, but not the least, we must also thank Cliff for taking us through a complex topic in a very engaging manner. Cliff certainly held the audience in rapt attention through an hour of highly technical discussion. The Q&A session was also very engaging. Of course, Cliff being the industry celebrity that he is, was mobbed by engineers asking questions after his speech. (This is a guest post for PuneTech by Arati Halbe, who has close to 9 years experience in ASIC front end design and verification. She is a PuneChips member.) As the complexity of Integrated Circuits (specifically ASIC and SoC) increases, and as their sizes keep reducing, the task of testing the chip gets more and more challenging. Engineers need to come up with better and different methodologies to ensure what goes to the factory for manufacturing is actually what they intended to deliver. Verification occurs at various stages in the ASIC development cycle. How much is enough at each stage is a problem that needs to be addressed on a case to case basis. A sound knowledge of various techniques and awareness of capabilities and limitations of each technique goes a long way in making decisions about when, where and what. (This is a guest blog by Chaitanya Rajguru, Associate Technical Fellow at KPIT Cummins, and a member of the PuneChips group.)
So where does one begin? One good starting point may be with a popular indicator used to gauge the “goodness” of EDA tool’s output: “Quality of Results”, or QoR. QoR is used as a higher-level indicator of process quality, much like a Customer Satisfaction Index that up-levels feedback on specific aspects such as timely delivery and responsiveness. IC design EDA tools have used to showcase what they can do. So is it possible to expand its scope to include “greenness” as well? Or is it just an attempt to paint a turkey blue and pass it off as a peacock? First, an update on PuneChips – we now have PuneChips Inaugural Event Well, I am quite excited to get the PuneChips forum up and running. While we would have liked to see more people attend, we had a good start. We invited most of the Semi/EDA folks in and around Pune and did get a very favorable response. Pending work and travel schedules are probably the culprits for a lower attendance, and I certainly hope that we will get more and more people to attend future events.
Continue reading Semiconductor Industry: Trends and Challenges |
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